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M12L2561616A2K Datasheet, PDF (5/45 Pages) Elite Semiconductor Memory Technology Inc. – JEDEC standard 3.3V power supply
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ESMT
M12L2561616A (2K)
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V ，TA = 0 to 70 °C )
Parameter
Value
Unit
Input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall-time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Version
Symbol
-5
-6
-7
Row active to row active delay
tRRD(min)
10
12
14
RAS to CAS delay
tRCD(min)
15
18
20
Row precharge time
tRP(min)
15
18
20
Row active time
tRAS(min)
40
42
45
tRAS(max)
100
@ Operating
tRC(min)
55
60
63
Row cycle time
@ Auto refresh tRFC(min)
55
60
70
Last data in to col. address delay
tCDL(min)
1
Last data in to row precharge
tRDL(min)
10
12
14
Last data in to burst stop
tBDL(min)
1
Refresh period (8,192 rows)
tREF(max)
64
Col. address to col. address delay tCCD(min)
1
Number of valid
CAS latency = 3
2
Output data
CAS latency = 2
1
Unit
Note
ns
1
ns
1
ns
1
ns
1
us
ns
1
ns
1,5
CLK
2
ns
1,2
CLK
2
ms
6
CLK
3
ea
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given tRFC after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with tRFCmin) can be posted to any given SDRAM, and the
maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x7.8 μ s.)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4
5/45
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