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M12L64164A2M Datasheet, PDF (36/45 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks
ESMT
M12L64164A (2M)
Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4
0
CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
CS
RAS
CAS
ADDR
Ra
Ca
BA0
Cb
Cc
BA1
A10/AP
Ra
DQ
WE
DQM
Row Active
Read
Qa0 Qa1
Qa2
Qa3
tSHZ
Clock
Supension
Read
Qb0 Qb1
tSHZ
Dc0
Dc2
*Note1
Read DQM
W rite
DQM
W rite
Clock
Suspension
Write
DQM
:Don't Care
*Note: 1. DQM is needed to prevent bus contention
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2012
Revision: 1.6
36/45