M52D256328A-2F Datasheet, PDF (30/46 Pages) Elite Semiconductor Memory Technology Inc. – LVCMOS compatible with multiplexed address

ESMT
M52D256328A (2F)
Power Up Sequence
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14 15
16 17
18
19
20
CLOCK
CKE
High level is necessary
CS
RAS
tRP
tRFC
tRFC
tMRD
tMRD
CAS
ADDR
BA1
BA0
A10/AP
DQ
High-Z
WE
DQM
High level is necessary
Key
Key
RA
BS
BS
RA
Precharge
(All Banks)
Auto Refresh
Auto Refresh
Mode Register Set
Row Active
Extended Mode
Register Set
: Don't care
Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)
- Apply V_DD before or at the same time as V_DDQ
- Apply V_DDQ
2. Start clock and maintain stable condition for a minimum.
3. The minimum of 200us after stable power and clock (CLK), apply NOP & take CKE high.
4. Issue precharge commands for all banks of the device.
5. Issue 2 or more auto-refresh commands.
6. Issue mode register set command to initialize the mode register.
7. Issue extended mode register set command to set PASR and DS.
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2014
Revision: 1.0
30/46