M52D256328A-2F Datasheet, PDF (1/46 Pages) Elite Semiconductor Memory Technology Inc. – LVCMOS compatible with multiplexed address

ESMT
Mobile SDRAM
FEATURES
 1.8V power supply
 LVCMOS compatible with multiplexed address
 Four banks operation
 MRS cycle with address key programs
- CAS Latency (3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
 EMRS cycle with address
 All inputs are sampled at the positive going edge of the
system clock
 Special function support
- PASR (Partial Array Self Refresh)
- TCSR (Temperature Compensated Self Refresh)
- DS (Driver Strength)
 DQM for masking
 Auto & self refresh
 64ms refresh period (4K cycle)
M52D256328A (2F)
2M x 32 Bit x 4 Banks
Mobile Synchronous DRAM
ORDERING INFORMATION
Product ID
Max Freq. Package Comments
M52D256328A-6BG2F 166MHz 90 Ball FBGA Pb-free
M52D256328A-7BG2F 143MHz 90 Ball FBGA Pb-free
GENERAL DESCRIPTION
The M52D256328A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by
32 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the
same device to be useful for a variety of high bandwidth, high performance memory system applications.
BALL CONFIGURATION (TOP VIEW)
(BGA 90, 8mmX13mmX1.2mm Body, 0.8mm Ball Pitch)
1
2
3 456 7
8
9
A DQ26 DQ24 VSS
VDD DQ23 DQ21
B DQ28 VDDQ VSSQ
VDDQ VSSQ DQ19
C VSSQ DQ27 DQ25
DQ22 DQ20 VDDQ
D VSSQ DQ29 DQ30
DQ17 DQ18 VDDQ
E VDDQ DQ31 NC
NC DQ16 VSSQ
F VSS DQM3 A3
A2 DQM2 VDD
G A4 A5 A6
A10 A0 A1
H A7 A8 NC
NC BA1 A11
J CLK CKE A9
BA0 CS RAS
K DQM1 NC NC
CAS WE DQM0
L VDDQ DQ8 VSS
VDD DQ7 VSSQ
M VSSQ DQ10 DQ9
DQ6 DQ5 VDDQ
N VSSQ DQ12 DQ14
DQ1 DQ3 VDDQ
P DQ11 VDDQ VSSQ
VDDQ VSSQ DQ4
R DQ13 DQ15 VSS
VDD DQ0 DQ2
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2014
Revision: 1.0
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