M12L32162A_0712 Datasheet, PDF (14/28 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16Bit x 2Banks Synchronous DRAM

ESMT
Read & Write Cycle at Same Bank @Burst Length = 4
M12L32162A
Operation Temperature Condition -40°C~105°C
0
CLOCK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
CKE
CS
RAS
CAS
tRCD
tRC ^*Note1
HIGH
*Note2
ADDR
Ra
Ca0
Rb
Cb0
BA
A10/AP
Ra
CL=2
QC
CL=3
WE
DQM
tRAC
*Note3
tRAC
*No te3
Rb
tOH
Qa0 Qa1 Qa2
tSAC
tOH
Qa0 Qa1
tSAC
Qa3
Qa2
tSHZ *Note4
Qa3
tSHZ _*Note4
Db0 Db1 Db2 Db3
tRDL
Db0 Db1 Db2 Db3
tRDL
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
W ri te
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note: 1.Minimum row cycle times is required to complete internal DRAM operation.
2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z(tSHZ) after the clock.
3.Access time from Row active command. tcc*(tRCD +CAS latency-1)+tSAC
4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
Burst can’t end in Full Page Mode.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.2
14/28