M14D5121632A Datasheet, PDF (12/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D5121632A
Parameter
Symbol
-2.5
Min.
Active to Precharge command
t_RAS
Active to Active command
(same bank)
t_RC
Auto Refresh row cycle time
t_RFC
Active to Read, Write delay
t_RCD
Precharge command period
t_RP
Active bank A to Active bank B
command
t_RRD
45
57.5 (-CL5)
60 (-CL6)
105
12.5 (-CL5)
15 (-CL6)
12.5 (-CL5)
15 (-CL6)
7.5
Write recovery time
t_WR
15
Write data in to Read command
delay
t_WTR
7.5
Col. address to Col. address
delay
t_CCD
2
Active to Auto Precharge delay
t_RAP
Average periodic Refresh
interval ( 0℃ ≦T_C ≦ +85℃ )
t_REFI
t_RCD(min.)
-
Average periodic Refresh
interval (+85℃ ＜T_C ≦ +95℃)
t_REFI
-
Write preamble
Write postamble
DQS Read preamble
DQS Read postamble
Load Mode Register / Extended
Mode Register cycle time
t_WPRE
t_WPST
t_RPRE
t_RPST
t_MRD
0.35
0.4
0.9
0.4
2
Auto Precharge write recovery
+ Precharge time
Internal Read to Precharge
command delay
t_DAL
WR+RU(t_WR / t_CK)
+(t_RP / t_CK (avg))
t_RTP
7.5
Exit Self Refresh to Read
command
t_XSRD
200
Exit Self Refresh to non-Read
command
t_XSNR
t_RFC + 10
Exit Precharge Power-Down to
any non-Read command
t_XP
2
Exit Active Power-Down to
Read command
t_XARD
2
Exit active power-down to Read
command
(slow exit / low power mode)
t_XARDS
8 - AL
CKE minimum pulse width
t_CKE
3
(high and low pulse width)
Max.
70K
-
-
-
-
-
-
-
-
-
7.8
3.9
-
0.6
1.1
0.6
-
-
-
-
-
-
-
-
-
-3
Min.
45
60
105
15
15
7.5
15
7.5
Max.
70K
-
-
-
-
-
-
-
2
-
t_RCD(min.)
-
-
7.8
-
3.9
0.35
-
0.4
0.6
0.9
1.1
0.4
0.6
2
-
WR+RU(t_WR / t_CK)
+(t_RP / t_CK (avg))
-
7.5
-
200
-
t_RFC + 10
-
2
-
2
-
7 - AL
-
3
-
Unit Note
ns
ns
ns
ns
ns
ns
ns
ns
t_CK
ns
us
us
t_CK (avg)
t_CK (avg)
t_CK (avg) 11
t_CK (avg) 12
t_CK
t_CK
1
ns
t_CK
ns
t_CK
t_CK
3
t_CK
2,3
t_CK
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
12/59