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M14D5121632A Datasheet, PDF (11/59 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks DDR II SDRAM
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ESMT
M14D5121632A
AC Timing Parameter & Specifications
Parameter
Symbol
-2.5
Min.
Max.
Clock period
CL=6
CL=5
tCK (avg)
2500
2500
8000
8000
DQ output access time from
CLK/ CLK
tAC
-400
+400
CLK high-level width
CLK low-level width
DQS output access time from
CLK/ CLK
tCH (avg)
tCL (avg)
tDQSCK
0.48
0.48
-350
0.52
0.52
+350
Clock to first rising edge of DQS
delay
tDQSS
Data-in and DM setup time
(to DQS)
tDS
(base)
Data-in and DM hold time
(to DQS)
tDH
(base)
DQ and DM input pulse width
(for each input)
tDIPW
Address and Control Input
setup time
tIS (base)
Address and Control Input hold
time
tIH (base)
Control and Address input pulse
width
tIPW
DQS input high pulse width
tDQSH
DQS input low pulse width
tDQSL
DQS falling edge to CLK rising
setup time
tDSS
DQS falling edge from CLK
rising hold time
tDSH
Data strobe edge to output data
edge
tDQSQ
Data-out high-impedance
window from CLK/ CLK
tHZ
-0.25
50
125
0.35
175
250
0.6
0.35
0.35
0.2
0.2
-
-
+0.25
-
-
-
-
-
-
-
-
-
-
200
tAC(max.)
Data-out low-impedance window tLZ
from CLK/ CLK
(DQS)
tAC(min.)
DQ low-impedance window from
CLK/ CLK
Half clock period
DQ/DQS output hold time from
DQS
tLZ
(DQ)
tHP
tQH
2 x tAC(min.)
Min
(tCL(abs),tCH(abs))
tHP-tQHS
DQ hold skew factor
tQHS
-
tAC(max.)
tAC(max.)
-
-
300
-3
Min.
-
3000
-450
0.48
0.48
-400
Max.
-
8000
+450
0.52
0.52
+400
-0.25
100
175
0.35
200
275
0.6
0.35
0.35
0.2
0.2
-
+0.25
-
-
-
-
-
-
-
-
-
-
240
-
tAC(max.)
tAC(min.)
tAC(max.)
2 x tAC(min.)
tAC(max.)
Min
(tCL(abs),tCH(abs))
-
tHP-tQHS
-
-
340
Unit Note
ps
13
ps
10
tCK (avg) 13
tCK (avg) 13
ps
10
tCK (avg)
ps
4
ps
5
tCK (avg)
ps
4
ps
5
tCK (avg)
tCK (avg)
tCK (avg)
tCK (avg)
tCK (avg)
ps
ps
10
ps
10
ps
10
ps 6,13
ps
ps
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
11/59
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