M52D128324A-2E Datasheet, PDF (10/31 Pages) Elite Semiconductor Memory Technology Inc. – LVCMOS compatible with multiplexed address

ESMT
M52D128324A (2E)
SIMPLIFIED TRUTH TABLE
COMMAND
A11
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP
Note
A9~A0
Register
Refresh
Mode Register Set
H
Extended Mode Register
Set
H
Auto Refresh
H
Entry
Self Refresh
Exit
L
XLL
L
L
X
XLL
L
L
X
H
LL
L
H
X
L
H
L
H
H
H
X
HX
X
X
OP CODE
1,2
OP CODE
1,2
3
X
3
3
X
3
Bank Active & Row Addr.
H
XLL
H
H
X
V Row Address
Read &
Auto Precharge Disable
Column Address _{Auto Precharge Enable}
H
Write & Column ^{Auto Precharge Disable}
Address
Auto Precharge Enable
H
Burst Stop
H
XLH
L
H
X
V
XLH
L
L
X
V
XLH
H
L
X
L ^Column 4
Address
H (A0~A7) 4,5
L ^Column 4
Address
H _(A0~A7) 4,5
X
6
Precharge
Bank Selection
All Banks
Clock Suspend or
Active Power Down Mode
Entry
Exit
H
XLL
H
L
X
V
L
X
H
4
X
4
H
L
H
X
X
X
X
LH
H
H
X
L
HXX
X
X
X
Entry
H
L
H
X
X
X
X
LH
H
H
Precharge Power Down Mode
X
HX
X
X
Exit
L
H
X
LH
H
H
DQM
H
X
V
X
7
No Operation Command
H
HX
X
X
X
X
H
LH
H
H
X
Deep Power Down Mode
Entry
H
L LH
H
L
X
X
Exit
L
HXX
X
X
X
(V= Valid, X= Don’t Care, H= Logic High, L = Logic Low)
Note:
1. OP Code: Operation Code
A0~A10/AP, A11, BA0~BA1: Program keys (@MRS). BA1 = 0 for MRS and BA1 = 1 for EMRS
2. MRS/EMRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS/EMRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto / self refresh can be issued only at all banks idle state.
4. BA0~BA1: Bank select addresses.
If both BA1 and BA0 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA1 is “Low” and BA0 is “High” at read, write, row active and precharge, bank B is selected.
If both BA1 is “High” and BA0 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA1 and BA0 are “High” at read, write, row active and precharge, bank D is selected
If A10/AP is “High” at row precharge, BA1 and BA0 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read / write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after (Read DQM latency is 2).
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
10/31