M24L416256SA Datasheet, PDF (1/14 Pages) Elite Semiconductor Memory Technology Inc. – 4-Mbit (256K x 16) Pseudo Static RAM

ESMT
M24L416256SA
PSRAM
4-Mbit (256K x 16) Pseudo Static RAM
Features
• Wide voltage range: 2.7V–3.6V
• Access time: 55 ns, 60 ns and 70 ns
• Ultra-low active power
— Typical active current: 1 mA @ f = 1 MHz
— Typical active current: 8 mA @ f = fmax (70-ns speed)
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The M24L416256SA is a high-performance CMOS Pseudo
static RAM organized as 256K words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode when
deselected ( CE HIGH or both BHE and BLE are HIGH).
The input/output pins (I/O0through I/O₁₅) are placed in a
high-impedance state when : deselected ( CE HIGH), outputs
are disabled ( OE HIGH), both Byte High Enable and Byte
Low Enable are disabled ( BHE , BLE HIGH), or during a write
operation ( CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip
Enable( CE LOW) and Write Enable ( WE ) input LOW. If Byte
Low Enable ( BLE ) is LOW, then data from I/O pins (I/O₀
through I/O₇) is written into the location specified on the
address pins(A₀ through A₁₇). If Byte High Enable ( BHE ) is
LOW, then data from I/O pins (I/O₈ through I/O₁₅) is written into
the location specified on the address pins (A₀ through A₁₇).
Reading from the device is accomplished by taking Chip
Enable ( CE LOW) and Output Enable ( OE ) LOW while
forcing the Write Enable ( WE ) HIGH. If Byte Low Enable
( BLE ) is LOW, then data from the memory location specified
by the address pins will appear on I/O₀ to I/O₇. If Byte High
Enable( BHE ) is LOW, then data from memory will appear on
I/O₈ toI/O₁₅. Refer to the truth table for a complete description
of read and write modes.
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.4
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