F25L08PA Datasheet, PDF (1/32 Pages) Elite Semiconductor Memory Technology Inc. – 3V Only 8 Mbit Serial Flash Memory with Dual

ESMT
Flash
F25L08PA
3V Only 8 Mbit Serial Flash Memory with Dual
„ FEATURES
y Single supply voltage 2.7~3.6V
y Standard, Dual SPI
y Speed
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz; 100MHz
- Fast Read Dual max frequency: 50MHz / 100MHz
(100MHz / 200MHz equivalent Dual SPI)
y Low power consumption
- Active current: 35 mA
- Standby current: 30 μ A
y Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
y Program
- Byte programming time: 7 μ s (typical)
- Page programming time: 1.5 ms (typical)
y Erase
- Chip erase time 10 sec (typical)
- Block erase time 1 sec (typical)
- Sector erase time 90 ms (typical)
y Page Programming
- 256 byte per programmable page
y Auto Address Increment (AAI) WORD Programming
- Decrease total chip programming time over
Byte Program operations
y Lockable 4K bytes OTP security sector
y SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
y End of program or erase detection
y Write Protect ( WP )
y Hold Pin ( HOLD )
y All Pb-free products are RoHS-Compliant
„ ORDERING INFORMATION
Product ID
F25L08PA –50PG
F25L08PA –100PG
F25L08PA –50PAG
F25L08PA –100PAG
F25L08PA –50DG
F25L08PA –100DG
Speed
50MHz
100MHz
50MHz
100MHz
50MHz
100MHz
Package
8 lead SOIC 150mil
8 lead SOIC 150mil
8 lead SOIC 200mil
8 lead SOIC 200mil
8 lead PDIP 300mil
8 lead PDIP 300mil
COMMENTS
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
„ GENERAL DESCRIPTION
The F25L08PA is a 8Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory
devices reliably store memory data even after 100,000
programming and erase cycles.
The memory array can be organized into 4,096 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction. The device also can be
programmed to decrease total chip programming time with Auto
Address Increment (AAI) programming.
The device features sector erase architecture. The memory array
is divided into 256 uniform sectors with 4K byte each; 16 uniform
blocks with 64K byte each. Sectors can be erased individually
without affecting the data in other sectors. Blocks can be erased
individually without affecting the data in other blocks. Whole chip
erase capabilities provide the flexibility to revise the data in the
device. The device has Sector, Block or Chip Erase but no page
erase.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.7
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