PBL40215 Datasheet, PDF (20/22 Pages) Ericsson – RF Transceiver circuit for the Digital Enhanced Cordless Telecommunications (DECT) system

PBL 402 15
IF Receiver.
The IF receiver consists of an upper sideband image reject down converter, a channel blocking filter, a limiting amplifier and
RSSI, an FM discriminator, a post detection filter and a data slicer.
The IF inputs are self biasing and have a balanced input impedance of 300 Ω. Matching to the external filter is required.
A band-pass filter provides additional channel selection and noise filtering prior to the limiting chain.
The quadrature based FM discriminator and post detection filter are self tuned to the required frequency by a slave PLL.
The FSK data is recovered by a threshold based data slicer. The slice level is determined up to the end of the 16 bit packet
preamble, where it should be held by an active SHOLD signal provided from the base-band controller. The slice controller determines
a more accurate level from this signal. An external capacitor is required on the DSL pin.
IF ReceiverTable.
Parameter
Frequency range
Input IP3
Input 1dB compression
Lower image suppression
Noise figure
Sensitivity
Input impedance
Input VSWR
Attenuation of channel M±1
Attenuation of channel M±2
Attenuation of channel M±3
Attenuation of channel M±4
Group delay deviation
Slice hold capacitor
Condition
Tested at ƒIF -23.5 MHz
Referenced to 300 Ω
BER = 10^-3
>ƒC ± 1.152 MHz
>ƒC ± 2.88 MHz
>ƒC ± 4.608 MHz
>ƒC ± 6.336 MHz
ƒC ± 576 kHz
On DSL pin to Gnd
Symbol
ƒIF
IP3
CP1
SSB
NF
SENS
ZIN
VSWRI
ATT1
ATT2
ATT3
ATT4
GDD
CDSL
Min.
-13
-15
29
-79
Typ.
110.6
-13
300
Max.
14
1.5:1
Unit
MHz
dBm
dBm
dB
dB
dBm
Ω
-
0.3
µs
2
nF
Demodulator
PLL
Synth. power on
Tx power on
Rx power on
SHOLD activated
R = 2k
R = 4k
12 x bit time @ (∼10.4µs)
Figure 11. Slice control.
R
R = 200k
LD
0
DRX
1
+
0
-
1
DRX_T
DSL
When the IF section is powered off, the DSL pin is tri-stated.
CDSL
20