S1D13305F00A100 Datasheet, PDF (52/266 Pages) Epson Company – Embedded 80K byte SRAM display buffer.

7: A.C. CHARACTERISTICS
Table 7-17 TFT/D-TFD A.C. Timing
Symbol
Parameter
Min.
Typ.
t1
Shift Pulse period
1
t2
Shift Pulse pulse width high
0.5
t3
Shift Pulse pulse width low
0.5
t4
Data setup to Shift Pulse falling edge
0.5
t5
Data hold from Shift Pulse falling edge
0.5
t6
Line Pulse cycle time
note 2
t7
Line Pulse pulse width low
9
t8
Frame Pulse cycle time
note 3
t9
Frame Pulse pulse width low
2t6
t10
Horizontal display period
note 4
t11
Line Pulse setup to Shift Pulse falling edge
0.5
t12
Frame Pulse falling edge to Line Pulse falling edge
phase difference
t6 - 18Ts
t13
DRDY to Shift Pulse falling edge setup time
0.5
t14
DRDY pulse width
note 5
t15
DRDY falling edge to Line Pulse falling edge
note 6
t16
DRDY hold from Shift Pulse falling edge
0.5
t17
Line Pulse Falling edge to DRDY active
note 7
Max.
250
Units
(note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
1. Ts = pixel clock period
2. t6_min = [((REG[04h] bits 6-0)+1) × 8 + ((REG[08h] bits 4-0)+4) × 8] Ts
3. t8_min = [((REG[06h] bits 1-0, REG[05h] bits 7-0)+1) + (REG[0Ah] bits 6-0)] Lines
4. t10_min = [((REG[04h] bits 6-0)+1) × 8] Ts
5. t14_min = [((REG[04h] bits 6-0)+1) × 8] Ts
6. t15_min = [(REG[07h] bits 4-0) × 8 + 16] Ts
7. t17_min = [(REG[08h] bits 4-0) - (REG[07]) × 8 + 16] Ts
S1D13705F00A HARDWARE FUNCTIONAL
SPECIFICATION (X27A-A-001-06)
EPSON
1-43