S1D13305F00A100 Datasheet, PDF (16/266 Pages) Epson Company – Embedded 80K byte SRAM display buffer.

4: FUNCTIONAL BLOCK DIAGRAM
4 FUNCTIONAL BLOCK DIAGRAM
Register
Generic MPU
MC68K
SH-3
SH-4
Host
I/F
40k × 16-bit SRAM
Memory
Controller
Power Save
Clocks
Look-Up
Table
LCD
I/F
LCD
Bus Clock
Memory Clock
Sequence Controller
Pixel Clock
Figure 4-1 System Block Diagram Showing Data Paths
4.1 Functional Block Descriptions
4.1.1 Host Interface
The Host Interface provides the means for the CPU/MPU to communicate with the display buffer
and internal registers.
4.1.2 Memory Controller
The Memory Controller arbitrates between CPU accesses and display refresh accesses. It also
generates the necessary signals to control the SRAM frame buffer.
4.1.3 Sequence Controller
The Sequence Controller controls data flow from the Memory Controller through the Look-Up Table
and to the LCD Interface. It also generates memory addresses for display refresh accesses.
4.1.4 Look-Up Table
The Look-Up Table contains three 256 × 4 Look-Up Tables or palettes, one for each primary color.
In monochrome mode only the green Look-Up Table is used.
S1D13705F00A HARDWARE FUNCTIONAL
SPECIFICATION (X27A-A-001-06)
EPSON
1-7