SRM20V100 Datasheet, PDF (3/8 Pages) Epson Company – 1M-Bit Static RAM

SRM20V100LLMX7
q AC Electrical Characteristics
r Read Cycle
Parameter
Read cycle time
Address access time
Chip select1 access time
Chip select2 access time
Output enable access time
Chip select1 output set time
Chip select1 output floating
Chip select2 output set time
Chip select2 output floating
Output enable output set time
Output enable output floating
Output hold time
Symbol
t_RC
t_ACC
t_ACS1
t_ACS2
t_OE
t_CLZ1
t_CHZ1
t_CLZ2
t_CHZ2
t_OLZ
t_OHZ
t_OH
Conditions
T1
T2
T1
(VDD = 2.7V to 3.6V, VSS = 0V, Ta = –25 to 85°C)
Min.
Max.
Unit
70
—
ns
—
70
ns
—
70
ns
—
70
ns
—
40
ns
5
—
ns
—
30
ns
5
—
ns
—
30
ns
0
—
ns
—
30
ns
10
—
ns
r Write Cycle
Parameter
Write cycle time
Chip select time1
Chip select time2
Address enable time
Address setup time
Write pulse width
Address hold time
Input data setup time
Input data hold time
WE Output floating
WE Output setup time
Symbol
t_WC
t_CW1
t_CW2
t_AW
t_AS
t_WP
t_WR
t_DW
t_DH
t_WHZ
t_OW
Conditions
T1
T2
(VDD = 2.7V to 3.6V, VSS = 0V, Ta = –25 to 85°C)
Min.
Max.
Unit
70
—
ns
60
—
ns
60
—
ns
60
—
ns
0
—
ns
55
—
ns
0
—
ns
30
—
ns
0
—
ns
—
30
ns
5
—
ns
T_{1 Test Conditions}
1. Input pulse level: 0.4V to 2.4V
2. tr = tf = 5ns
3. Input and output timing reference
levels : 1.5V
I/O
4. Output load CL = 100pF
+3V
1.0kΩ
CL
920Ω
CL=100pF (Includes Jig Capacitance)
T_{2 Test Conditions}
1. Input pulse level : 0.4V to 2.4V
+3V
2. tr = tf = 5ns
3. Input timing reference levels: 1.5V
1.0kΩ
4. Output timing reference levels:
I/O
±200mV (the level displaced from
stable output voltage level)
CL
920Ω
5. Output load CL = 5pF
CL=5pF (Includes Jig Capacitance)
3