SRM20V100 Datasheet, PDF (1/8 Pages) Epson Company – 1M-Bit Static RAM

PF805-04
SRM20^SV^RM1²0⁰0^V1L⁰L^0LM^LMX^X7⁷
1M-Bit Static RAM
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q Low Supply Voltage
q Wide Temperature Range
q Low Supply Current
s DESCRIPTION
q Access Time 70ns (2.7V)
q 131,072 Words×8-Bit Asynchronous
The SRM20V100LLMX7 is an 131,072 words×8-bit asynchronous, static, random access memory on a monolithic
CMOS chip. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage
with back-up batteries. And —25 to 85°C operating temperature range makes it ideal for portable equipment.
The asynchronous and static nature of the memory requires no external clock or refreshing circuit. Both the
input and output ports are TTL compatible and 3-state output allows easy expansion of memory capacity.
s FEATURES
q Wide temperature range ..... –25 to 85°C
q Fast Access time ................. SRM20V100LLMX7 70ns (Max.)
q Low supply current .............. standby: 0.6µA (Typ.): LL Version
0.3µA (Typ.): SL Version
operation: 8mA/1MHz (Typ.)
q Completely static ................. No clock required
q Supply voltage..................... 2.7V to 3.6V
q TTL compatible inputs and outputs
q 3-state output with wired-OR capability
q Non-volatile storage with back-up batteries
s PIN CONFIGURATION
(SOP6)
N.C. 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/01 13
I/02 14
I/03 15
VSS 16
32 VDD
31 A15
30 CS2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CS1
21 I/08
20 I/07
19 I/06
18 I/05
17 I/04
q Package ...... SRM20V100LLMX7 SOP6-32pin (plastic)
SRM20V100LLTX7 TSOP ( I )-32pin (plastic)
(TSOP/Slim-TSOP)
SRM20V100LLRX7
SRM20V100LLKX7
SRM20V100LLYX7
s BLOCK DIAGRAM
TSOP ( I )-32pin-R1 (plastic)
Slim-TSOP ( I )-32pin (plastic)
Slim-TSOP ( I )-32pin-R1 (plastic)
A11 1
A9 2
A8 3
A13 4
WE 5
CS2 6
A15 7
VDD 8
N.C. 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
SRM20V100LLTX/KX
32 OE
31 A10
30 CS1
29 I/08
28 I/07
27 I/06
26 I/05
25 I/04
24 VSS
23 I/03
22 I/02
21 I/01
20 A0
19 A1
18 A2
17 A3
A0
A1
A2
A3
A4
10
1024
Memory Cell Array
A5
1024×128×8
A6
A7
A8
A9
A10
A11
128×8
A12
A13
7
128
Column Gate
A14
A15
A16
(TSOP-R1/Slim-TSOP-R1)
A4 16
A5 15
A6 14
A7 13
A12 12
A14 11
A16 10
N.C. 9
VDD 8
A15 7
CS2 6
WE 5
A13 4
A8 3
A9 2
A11 1
SRM20V100LLRX/YX
17 A3
18 A2
19 A1
20 A0
21 I/01
22 I/02
23 I/03
24 VSS
25 I/04
26 I/05
27 I/06
28 I/07
29 I/08
30 CS1
31 A10
32 OE
CS1
8
¡PIN DESCRIPTION
CS2
A0 to A16 Address Input
WE
Write Enable
OE
OE
Output Enable
I/O Buffer
CS1, CS2 Chip Select
WE
I/O1 to I/O8 Data I/O
VDD
Power Supply (2.7V to 3.6V)
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
VSS
N. C.
Power Supply (0V)
No connection
1