S1D15714 Datasheet, PDF (15/65 Pages) Epson Company – a single chip MLS driver

S1D15714 Series
CS
SI
SCL
A0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Fig. 6.1
* When the chip is inactive, the counter is reset to the initials state.
* Reading is not performed in the case of serial interface.
* For the SCL signal, a sufficient care must be taken against terminal reflection of the wiring and external noise.
Recommend to use an actual equipment to verify the operation.
6.1.4 Chip Selection
The S1D15714 Series has chip select pin. MPU interface or serial interface is enabled only when CS = LOW.
When the chip select pin is inactive, D0 to D5 are in the state of high impedance, while A0, RD and WR inputs are
disabled. When serial interface is selected, the shift register and counter are reset.
6.1.5 Access to display data RAM and internal register
Access to S1D15714 Series series viewed from the MPU side is enabled only if the cycle time requirements are kept.
This does not required waiting time; hence, high-speed data transfer is allowed.
Furthermore, at the time of data transfer with the MPU, S1D15714 Series provides a kind of inter-LSI pipe line
processing via the bus holder accompanying the internal data bus.
For example, when data is written to the display data RAM by the MPU, the data is once held by the bus holder. It is
written to the display data RAM before the next data write cycle comes.
On the other hand, when the MPU reads the content of the display data RAM, it is read in the first data read cycle
(dummy), and the data is held in the bus holder. Then it is read onto on the system bus from the bus holder in the next
data read cycle. Restrictions are imposed on the display data RAM read sequence. When the address has been set,
specified address data is not output to the Read command immediately after that. The specified address data is output
in the second data reading. This must be carefully noted. Therefore, one dummy read operation is mandatory
subsequent to address setting or write cycle. Fig. 6.2 illustrates this relationship.
12
EPSON
Rev. 1.0