EM47FM0888MBA_15 Datasheet, PDF (16/38 Pages) Eorex Corporation – Double DATA RATE 3 low voltage SDRAM

EM47FM0888MBA
AC Operating Test Characteristics
VDD/VDDQ = 1.35V(1.283-1.45V)
Symbol
Speed Bin
CL-nRCD-nRP
-125
(DDR3-1600)
11-11-11
Parameter
Min. Max.
tCK
Minimum clock cycle, DLL-off mode
8
-
tCH, tCL (AVG) Average CK high/low level width
0.47 0.53
tRRD
Active bank A to active bank B
command period
6
-
4
-
tFAW
Four Activate Window
30
-
tIH(base) Address and Control input hold time
120
-
DC100 (VIH/VIL(DC100) levels)
tIS(base) Address and Control input setup time
45
-
AC175 (VIH/VIL(AC175) levels)
tIS(base) Address and Control input setup time ₄₅₊₁₂₅
-
AC150 (VIH/VIL(AC150) levels)
tDH(base)
DQ and DM input hold time
(VIH/VIL(DC) levels)
45
-
tDS(base)
DQ and DM input setup time
(VIH/VIL(AC) levels)
10
-
tIPW
Address and control input pulse width ₅₆₀
for each input
-
tDIPW
DQ and DM input pulse width for
each input
360
-
tHZ(DQ) DQ high impedance time
-
225
tLZ(DQ) DQ low impedance time
-450 225
DQS,/DQS high impedance time
tHZ(DQS)
RL+BL/2 reference
-
225
tLZ(DQS)
DQS,/DQS low impedance time
RL-1 reference
-450 225
tDQSQ
DQS,/DQS to DQ skew per group,
per access
-
100
tCCD
/CAS to /CAS command delay
4
-
tQH
DQ output hold time from DQS, /DQS 0.38
-
tDQSCK
tDQSS
DQS,/DQS rising edge output access _-225
225
time from rising CK,/CK
DQS latch rising transitions to
associated clock edges
-0.27 0.27
tDQSH
DQS input high pulse width
0.45 0.55
-150
(DDR3-1333)
9-9-9
Min. Max.
8
-
0.47 0.53
6
-
4
-
30
-
140
-
-187
(DDR3-1066)
7-7-7
Min. Max.
8
-
0.47 0.53
6
-
4
-
30
-
Units
ns
ns
ns
nCK
ns
Notes
6
160
-
ps
16
65
-
85
-
ps
16
65+150 - 85+178 -
ps 16,24
65
-
85
-
ps
17
10
-
10
-
ps
17
620
-
780
-
ps
25
400
-
490
-
250 -
300
-500 250 -600 300
-
250 -
300
ps
25
ps 13,14
ps 13,14
ps 13,14
-500 250 -600 300 ps 13,14
-
4
0.38
-255
-0.25
0.45
125
-
-
255
0.25
0.55
-
4
0.38
-225
-0.25
0.45
150 ps 12,13
-
nCK
-
tCK _12,13
(avg)
255 ps 12,13
0.25
0.55
tCK
(avg)
tCK
(avg)
27,28
Apr. 2014
16/38
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