EM47FM1688MCA_15 Datasheet, PDF (10/39 Pages) Eorex Corporation – Double DATA RATE 3 SDRAM

EM47FM1688MCA/SCA
Note that while Address/command and DQ signal requirements are with respect to VREF, the single-ended
components of differential signals have a requirement with respect to VDD/2; this is nominally the same.
The transition of single-ended signals through the AC-levels is used to measure setup time. For singleended
components of differential signals the requirement to reach VSEL max, VSEH min has no bearing on timing, but
adds a restriction on the common mode characteristics of these signals.
Single-ended levels for CK, DQS, /CK, /DQS
Symbol
VSEH
VSEL
Parameter
Single-ended high-level for strobes
Single-ended high-level for CK, /CK
Single-ended low-level for strobes
Single-ended low-level for CK, /CK
Min.
(VDD/2)+0.175
(VDD/2)+0.175
See Note3
See Note3
Max.
See Note3
See Note3
(VDD/2)-0.175
(VDD/2)-0.175
Units
V
V
V
V
Note
1,2
1,2
1,2
1,2
Note1. For CK, /CK use VIH/VIL(AC) of address/command; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs.
Note2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for address/command is based on
VREFCA; if a reduced AC-high or AC-low level is used for a signal group, then the reduced level
applies also here.
Note3. These values are not defined, however the single-ended components of differential signals CK, /CK,
DQS, /DQS need to be within the respective limits (VIH(DC) max, VIL(DC) min) for single-ended signals
as well as the limitations for overshoot and undershoot.
Jul. 2014
10/39
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