EM47FM1688MCA_15 Datasheet, PDF (1/39 Pages) Eorex Corporation – Double DATA RATE 3 SDRAM

EM47FM1688MCA/SCA
8Gb (32M×8Bank×16×2Rank) Double DATA RATE 3 SDRAM
Features
Description
• Use Two 256M x 16 dies stack to 256M x 16 x 2R DDP. ^{The EM47FM1688MCA/SCA is a high speed Double}
• VDD/VDDQ = 1.35V -0.065/+0.1V
• Backward compatible to VDD/ VDDQ = 1.5V ±0.075V.
• All inputs and outputs are compatible with SSTL_15
Date Rate 3 (DDR3) low voltage Synchronous DRAM
fabricated with ultra high performance CMOS
interface.
process containing 8G(8,196M) bits which
• Fully differential clock inputs (CK, /CK) operation.
• Eight Banks
• Posted CAS by programmable additive latency
organized as 32Mb x 8 banks x 2R by 16 bits. This
synchronous device achieves high speed
• Bust length: 4 with Burst Chop (BC) and 8.
• CAS Write Latency (CWL): 5, 6, 7, 8
• CAS Latency (CL): 6, 7, 8, 9, 10, 11
double-data-rate transfer rates of up to 1600
Mb/sec/pin (DDR3-1600) for general applications.
• Write Latency (WL) =Read Latency (RL) -1.
The chip is designed to comply with the following key
• Bi-directional Differential Data Strobe (DQS).
• Data inputs on DQS centers when write.
• Data outputs on DQS, /DQS edges when read.
DDR3 SDRAM features: (1) posted CAS with
additive latency, (2) write latency = read latency -1,
• On chip DLL align DQ, DQS and /DQS transition
with CK transition.
• DM mask write data-in at the both rising and falling
(3) On Die Termination, (4) programmable driver
strength data,(5) seamless BL4 access with
edges of the data strobe.
bank-grouping. All of the control and address inputs
• Sequential & Interleaved Burst type available both
for 8 & 4 with BC.
• Multi Purpose Register (MPR) for pre-defined
are synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross
pattern read out
• On Die Termination (ODT) options: Synchronous
ODT, Dynamic ODT, and Asynchronous ODT
• Auto Refresh and Self Refresh
point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional
differential data strobes (DQS and /DQS) in a source
• 8,192 Refresh Cycles / 64ms
• Refresh Interval: 7.8us Tcase between 0°C ~ 85°C
• Refresh Interval: 3.9us Tcase between 85°C ~ 95°C
• RoHS Compliance
synchronous fashion. The address bus is used to
convey row, column and bank address information in
a /RAS and /CAS multiplexing style. The 8Gb DDR3
• Pb-Free
• Driver Strength: RZQ/7, RZQ/6(RZQ=240Ω)
• High Temperature Self-Refresh rate enable
• ZQ calibration for DQ drive and ODT
devices operates with a single power supply:
1.35V -0.065/+0.1V & 1.5V ±0.075V VDD and VDDQ.
Available package: FBGA-96Ball (with 0.8mm x 0.8mm
• RESET pin for initialization and reset function
ball pitch)
Jul. 2014
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