EN25LF40_1 Datasheet, PDF(9/35 Page) Eon Silicon Solution Inc. – 4 Megabit Serial Flash Memory with 4Kbytes Uniform Sector

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EN25LF40_1 Datasheet, PDF (9/35 Pages) Eon Silicon Solution Inc. – 4 Megabit Serial Flash Memory with 4Kbytes Uniform Sector

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INSTRUCTIONS

EN25LF40

All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial

Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is driven

Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on

Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).

The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code.

Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or

none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has been

shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),

Read Status Register (RDSR) or Release from Deep Power-down, and Read Device ID (RDI)

instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#)

can be driven High after any bit of the data-out sequence is being shifted out.

In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write

Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)

instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction

is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock

pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at

any time the input byte is not a full byte, nothing will happen and WEL will not be reset.

In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down

(RES ) minimum number of bytes specified has to be given, without which, the command will be

ignored.

In the case of Page Program, if the number of byte after the command is less than 4 (at least 1

data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must, any

less or more will cause the command to be ignored.

All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase

cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues

unaffected.

Table 4. Instruction Set

Instruction Name

Byte 1

Code

Byte 2

Byte 3

Byte 4 Byte 5 Byte 6

n-Bytes

Write Enable

06h

Write Disable / Exit

OTP mode

04h

Read Status

05h

Write Status

01h

Read Data

03h

Fast Read

0Bh

Page Program

02h

Sector Erase / OTP

erase

20h

Block Erase

D8h

(S7-S0)(1)

S7-S0

A23-A16

A15-A8

A23-A16 A15-A8

continuous(2)

A7-A0

(D7-D0)

dummy

D7-D0

(Next byte)

(D7-D0)

Next byte

continuous

(Next Byte)

continuous

Chip Erase

C7h/ 60h

Deep Power-down B9h

Release from Deep

(3)

Power-down, and

dummy

dummy dummy (ID7-ID0)

read Device ID

ABh

Release from Deep

Power-down

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. G, Issue Date: 2010/05/31

www.eonssi.com

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