EN25F40A Datasheet, PDF (53/62 Pages) Eon Silicon Solution Inc. – 4 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25F40A
Table 14. AC Characteristics
(T_a = - 40°C to 85°C; V_CC = 2.7-3.6V)
Symbol Alt
Parameter
Min
Typ
Max
Serial Clock Frequency for:
FAST_READ, PP, QPP, SE, HBE, BE, DP, RES, D.C.
-
104
F_R
f_C
WREN, WRDI, WRSR, RDSR
Serial Clock Frequency for:
RDID, Dual Output Fast Read and Quad I/O Fast D.C.
-
104
Read
f_R
t_CH ¹
t_CL1
t_CLCH2
t_CHCL ²
Serial Clock Frequency for READ
Serial Clock High Time
Serial Clock Low Time
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
D.C.
-
50
4
-
-
4
-
-
0.1
-
-
0.1
-
-
t_SLCH
t_{CSS CS# Active Setup Time (Relative to CLK)}
5
-
-
t_CHSH
CS# Active Hold Time (Relative to CLK)
5
-
-
t_SHCH
CS# Not Active Setup Time (Relative to CLK)
5
-
-
t_CHSL
CS# Not Active Hold Time (Relative to CLK)
5
-
-
t_SHSL
t_CSH
CS# High Time for read
CS# High Time for program/erase
7
30
-
-
t_SHQZ ²
t_CLQX
t_DVCH
t_CHDX
t_HLCH
t_HHCH
t_CHHH
t_CHHL
t_HLQZ ²
t_HHQX ²
t_CLQV
t_WHSL3
t_SHWL3
t_DP ²
t_RES1 ²
t_RES2 ²
t_W
t_PP
t_SE
t_HBE
t_BE
t_CE
t_{DIS Output Disable Time}
t_{HO Output Hold Time}
t_{DSU Data In Setup Time}
t_{DH Data In Hold Time}
HOLD# Low Setup Time ( relative to CLK )
HOLD# High Setup Time ( relative to CLK )
HOLD# Low Hold Time ( relative to CLK )
HOLD# High Hold Time ( relative to CLK )
t_{HZ HOLD# Low to High-Z Output}
t_{LZ HOLD# High to Low-Z Output}
t_V
Output Valid from CLK for 30 pF
Output Valid from CLK for 15 pF
Write Protect Setup Time before CS# Low
Write Protect Hold Time after CS# High
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic
Signature read
CS# High to Standby Mode with Electronic
Signature read
Write Status Register Cycle Time
Page Programming Time
Sector Erase Time
32KB Block Erase Time
64KB Block Erase Time
Chip Erase Time
-
-
6
0
-
-
2
-
-
5
-
-
5
5
5
5
6
6
-
-
8
6
20
-
-
100
-
-
-
-
3
-
-
3
-
-
1.8
-
2
15
-
0.8
3
-
0.03
0.2
0.1
0.8
-
0.2
1
-
1.5
7.5
t_SR
Software Reset ^{WIP = write operation}
-
-
28
Latency
WIP = not in write operation
-
-
0
Note: 1. t_CH + t_CL must be greater than or equal to 1/ f_C
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write status Register instruction when Status Register Protect Bit is set at 1.
Unit
MHz
MHz
MHz
ns
ns
V / ns
V / ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
ms
ms
s
s
s
s
µs
µs
This Data Sheet may be revised by subsequent versions
53
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc.,
Rev. A, Issue Date: 2013/11/18
www.eonssi.com