EN25Q32A Datasheet, PDF (26/52 Pages) Eon Silicon Solution Inc. – 32 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25Q32A
Figure 14.1. Quad Input / Output Fast Read Instruction Sequence under EQIO Mode
Another sequence of issuing Quad Input/Output FAST_READ (EBh) instruction especially useful in
random access is : CS# goes low -> sending Quad Input/Output FAST_READ (EBh) instruction -> 24-
bit address interleave on DQ₃, DQ₂, DQ₁ and DQ₀ -> performance enhance toggling bit P[7:0] -> 4
dummy cycles -> data out interleave on DQ₃, DQ₂, DQ₁ and DQ₀ till CS# goes high -> CS# goes low
(reduce Quad Input/Output FAST_READ (EBh) instruction) -> 24-bit random access address, as shown
in Figure 15.
In the performance – enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0] = A5h, 5Ah,
F0h or 0Fh can make this mode continue and reduce the next Quad Input/Output FAST_READ (EBh)
instruction. Once P[7:4] is no longer toggling with P[3:0] ; likewise P[7:0] = FFh, 00h, AAh or 55h. And
afterwards CS# is raised, the system then will escape from performance enhance mode and return to
normal operation.
While Program/ Erase/ Write Status Register is in progress, Quad Input/Output FAST_READ (EBh)
instruction is rejected without impact on the Program/ Erase/ Write Status Register current cycle.
The instruction sequence is shown in Figure 15.1 while using the Enable Quad I/O (EQIO) (38h) command.
This Data Sheet may be revised by subsequent versions
26
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com