EN25QH16A Datasheet, PDF (22/66 Pages) Eon Silicon Solution Inc. – 16 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25QH16A
64KB-Block/Sector switch bit (S4)
This bit is set by WRSR command in OTP mode. It is used to set the protection area size as block
(64KB) or sector (4KB).
Top/Bottom switch bit (S6)
This bit is set by WRSR command in OTP mode. It is used to set the protected 64KB-Block/Sector
location to the top/bottom in the device.
OTP_LOCK bit. (S7)
This bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as normal sector while
OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR command, the OTP
sector is protected from program and erase operation. The OTP_LOCK bit can only be programmed
once.
Write Status Register (WRSR) (01h)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write
Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by
the instruction code and the data byte on Serial Data Input (DI).
The instruction sequence is shown in Figure 11. The Write Status Register (WRSR) instruction has no
effect on S1 and S0 of the Status Register. Chip Select (CS#) must be driven High after the eighth bit of
the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register cycle (whose
duration is t_W) is initiated. While the Write Status Register cycle is in progress, the Status Register may
still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is
completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect
(BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table 3. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register
Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected
Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware
Protected Mode (HPM) is entered.
The instruction sequence is shown in Figure 11.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
NOTE :
In the OTP mode, WRSR command is used to program OTP_LOCK bit, TB bit, 4KB BL bit and EBL bit
to ‘1‘, but these bits only can be programmed once.
This Data Sheet may be revised by subsequent versions
22
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc.,
Rev. A, Issue Date: 2013/11/25
www.eonssi.com