EN25Q16B Datasheet, PDF (21/62 Pages) Eon Silicon Solution Inc. – 16 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

Table 7.2 Status Register Bit Locations (In OTP mode)
EN25Q16B
S7
OTP_LOCK bit
S6
TB bit
(Top / Bottom
Protect)
S5
S4
S3
4KB BL bit
(4KB boot lock)
EBL bit
(Enable boot lock)
S2
S1
S0
WEL bit
WIP bit
(Write Enable (Write In
Latch)
Progress bit)
1 = OTP sector
is protected
1 = Bottom
0 = Top
(default 0)
none
1 = Sector
0 = 64KB Block
(default 0)
1 = Permanent lock
selected 64KB-
Block/Sector
none
1 = write
enable
0 = not write
enable
1 = write
operation
0 = not in write
operation
OTP bit
OTP bit
OTP bit
OTP bit
Read only bit Read only bit
Note
1. In OTP mode, S7 bit is served as OTP_LOCK bit; S6 bit is served as TB bit; S4 bit is served as 4KB BL bit; S3 bit is
served as EBL bit; S1 bit is served as WEL bit and S0 bit is served as WIP bit.
2. See the table 3 “Protected Area Sizes Sector Organization”.
The status and control bits of the Status Register are as follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Status Register, Program or Erase instruction is accepted.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define
the size of the area to be software protected against Program and Erase instructions. These bits are
written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP3,
BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected
against Page Program (PP) Sector Erase (SE) and , Block Erase (BE), instructions. The Block Protect
(BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.
The Chip Erase (CE) instruction is executed if, and only if, all Block Protect (BP3, BP2, BP1, BP0) bits
are 0.
WPDIS bit. The Write Protect disable (WPDIS) bit, non-volatile bit, when it is reset to “0” (factory
default) to enable WP# function or is set to “1” to disable WP# function. No matter WPDIS is “0＂ or
“1＂, the system can executes Quad Input/Output FAST_READ (EBh) or EQPI (38h) command
directly. User can use Flash Programmer to set WPDIS bit as “1＂ and then the host system can let
WP# keep floating in SPI mode.
SRP bit / The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect (WP#)
signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow the device to
be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set to 1, and
Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register (SRP, BP3,
BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer
accepted for execution.
In OTP mode, S7, S6, S4, S3, S1 and S0 are served as OTP_Lock Bit, TB bit, 4KB BL bit, EBL, WEL
and WIP bit.
Enable Boot Lock bit (S3)
When this bit is programmed to ‘1’ by WRSR command in OTP mode, the Top/Bottom switch bit and
64KB-Block/Sector switch bit and the selected sector/block will be permanent locked. The Enable Boot
Lock bit can only be programmed once.
This Data Sheet may be revised by subsequent versions
21
or modifications due to changes in technical specifications.
©2014 Eon Silicon Solution, Inc.,
Rev. A, Issue Date: 2014/03/14
www.eonssi.com