EN25Q16B Datasheet, PDF (10/62 Pages) Eon Silicon Solution Inc. – 16 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25Q16B
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and
a Page Program (PP) or Quad Input Page Program (QPP) sequence, which consists of four bytes plus
data. This is followed by the internal Program cycle (of duration t_PP).
To spread this overhead, the Page Program (PP) or Quad Input Page Program (QPP) instruction allows
up to 256 bytes to be programmed at a time (changing bits from 1 to 0) provided that they lie in
consecutive addresses on the same page of memory.
Sector Erase, Half Block Erase, Block Erase and Chip Erase
The Page Program (PP) or Quad Input Page Program (QPP) instruction allows bits to be reset from 1 to
0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can
be achieved a sector at a time, using the Sector Erase (SE) instruction, half a block at a time using the
Half Block Erase (HBE) instruction, a block at a time using the Block Erase (BE) instruction or
throughout the entire memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle
(of duration t_SE, t_HBE, t_BE or t_CE). The Erase instruction must be preceded by a Write Enable (WREN)
instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP, QPP) or Erase (SE,
HBE, BE or CE) can be achieved by not waiting for the worst case delay (t_W, t_PP, t_SE, t_HBE, t_BE or t_CE). The
Write In Progress (WIP) bit is provided in the Status Register so that the application program can
monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is
complete.
Active Power, Stand-by Power and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip
Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal
cycles have completed (Program, Erase, and Write Status Register). The device then goes into the
Stand-by Power mode. The device consumption drops to I_CC1.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down
Mode (DP) instruction) is executed. The device consumption drops further to I_CC2. The device remains
in this mode until another specific instruction (the Release from Deep Power-down Mode and Read
Device ID (RDI) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used
as an extra software protection mechanism, when the device is not in active use, to protect the device
from inadvertent Write, Program or Erase instructions.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the
EN25Q16B provides the following data protection mechanisms:
z Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes
while the power supply is outside the operating specification.
z Program, Erase and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set
the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP), Quad Input Page Program (QPP) instruction completion or
Sector Erase (SE) instruction completion or Half Block Erase (HBE) / Block Erase (BE)
instruction completion or Chip Erase (CE) instruction completion
z The Block Protect (BP3, BP2, BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the Software Protected Mode (SPM).
z The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status
Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
z In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all instructions are
ignored except one particular instruction (the Release from Deep Power-down instruction).
This Data Sheet may be revised by subsequent versions
10
or modifications due to changes in technical specifications.
©2014 Eon Silicon Solution, Inc.,
Rev. A, Issue Date: 2014/03/14
www.eonssi.com