EN25QH32A Datasheet, PDF (17/63 Pages) Eon Silicon Solution Inc. – 32 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25QH32A
Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit. The Write
Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Half Block
Erase (HBE), Block Erase (BE), Chip Erase (CE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the
instruction code, and then driving Chip Select (CS#) High.
The instruction sequence is shown in Figure 9.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 8. Write Enable Instruction Sequence Diagram
Write Disable (WRDI) (04h)
The Write Disable instruction (Figure 9) resets the Write Enable Latch (WEL) bit in the Status Register
to a 0 or exit from OTP mode to normal mode. The Write Disable instruction is entered by driving Chip
Select (CS#) low, shifting the instruction code “04h” into the DI pin and then driving Chip Select (CS#)
high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write
Status Register, Page Program, Sector Erase, Half Block Erase (HBE), Block Erase (BE) and Chip
Erase instructions.
The instruction sequence is shown in Figure 9.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 9. Write Disable Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc.,
Rev. A, Issue Date: 2013/11/25
www.eonssi.com