EN71SN2BGD11 Datasheet, PDF (121/125 Pages) Eon Silicon Solution Inc. – 1.8V NAND Flash + 1.8V Mobile DDR SDRAM Multi-Chip Package

EN71SN2BGD11
SELF REFRESH
SELF REFRESH command can be used to retain data in the Mobile DDR SDRAM, even if the rest of
the system is powered down. When in the self refresh mode, the Mobile DDR SDRAM retains data
without external clocking. The Mobile DDR SDRAM device has a built-in timer to accommodate Self
Refresh operation. The SELF REFRESH command is initiated like an AUTO REFRESH command,
except CKE is LOW. Input signals except CKE are “Don’t Care” during Self Refresh. During SELF
REFRESH, the device is refreshed as identified in the extended mode register. Once the SELF
REFRESH command is registered, the external clock can be halted after one clock later. CKE must be
held low to keep the device in Self Refresh mode, and internal clock also disabled to save power. The
minimum time that the device must remain in Self Refresh mode is tRFC.
In the Self Refresh mode, two additional power-saving options exist: Temperature Compensated Self
Refresh and Partial Array Self Refresh. During this mode, the device is refreshed as identified in the
extended mode register. An internal temperature sensor will adjust the refresh rate to optimize device
power consumption while ensuring data integrity. During SELF REFRESH operation, refresh intervals
are scheduled internally and may vary. These refresh intervals may be different then the specified tREFI
time. For this reason, the SELF REFRESH command must not be used as a substitute for the AUTO
REFRESH command.
The procedure for exiting SELF REFRESH requires a sequence of commands. First, CK must be stable
prior to CKE going back HIGH. When CKE is HIGH, the Mobile DDR SDRAM must have NOP
commands issued for tXSR time to complete any internal refresh already in progress. Self Refresh is to
be supported for full AT temperature range up to 105℃. A temperature trip point should be provided to
achieve 4x refresh rate above 85℃.
Notes:
1. Clock must be stable, cycling within specifications by Ta0, before exiting self refresh mode.
2. Device must be in the all banks idle state prior to entering self refresh mode.
3. NOPs or DESELECTs is required for tXSR time with at least two clock pulses.
4. AR = AUTO REFRESH.
5. CKE must remain LOW to remain in self refresh.
This Data Sheet may be revised by subsequent versions
121
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/11/29