EN71SN2BGD11 Datasheet, PDF (1/125 Pages) Eon Silicon Solution Inc. – 1.8V NAND Flash + 1.8V Mobile DDR SDRAM Multi-Chip Package

EN71SN2BGD11
EN71SN2BGD11
1.8V NAND Flash + 1.8V Mobile DDR SDRAM Multi-Chip Package
Features
• Multi-Chip Package
- NAND Flash Density: 2-Gbits
- Mobile DDR SDRAM Density: 1-Gbits
• Device Packaging
- 137 balls BGA
Area: 10.5x13 mm; Height: 1.2 mm
- 130 balls BGA
Area: 8x9 mm; Height: 1.0 mm
• Operating Voltage
- NAND : 1.7V to 1.95V
- Mobile DDR SDRAM : 1.7V to 1.95V
• Operating Temperature :-25 °C to +85 °C
NAND FLASH
Mobile DDR SDRAM
• Voltage Supply: 1.7V ~ 1.95V
• Organization
- Memory Cell Array :
(256M + 8M) x 8bit for 2Gb
- Multiplexed address/ data
- Data Register : (2K + 64) x 8bit
• Automatic Program and Erase
- Page Program : (2K + 64) bytes
- Block Erase : (128K + 4K) bytes
• Page Read Operation
- Page Size : (2K + 64) bytes
- Random Read : 25µs (Max.)
- Serial Access : 45ns (Min.)
• Memory Cell: 1bit/Memory Cell
• Fast Write Cycle Time
- Page Program Time : 250µs (Typ.)
- Block Erase Time : 2ms (Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power
Transitions
• Reliable CMOS Floating-Gate Technology
- ECC Requirement: 4 bit/512 bytes
- Endurance: 100K Program/Erase Cycles
- Data Retention: 10 Years
• Command Register Operation
• Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
• NOP: 4 cycles
• Cache Program/Read Operation
• Copy-Back Operation
• Two-plane Operation
• EDO mode
• Bad-Block-Protect
• Density: 1G bits
• Organization: 8M words x 32 bits x 4 banks
• Power supply: V_DD/V_DDQ= 1.70~1.95V
• Four internal banks for concurrent operation
• 1.8V LVCMOS-compatible inputs
• Programmable Burst Lengths : 2, 4, 8 or 16
• Burst Type : Sequential and Interleave
• Auto Refresh and Self Refresh Modes
• Configurable Drive Strength (DS)
• Optional Partial Array Self Refresh (PASR)
• On-chip temperature sensor to control self
refresh rate Temperature Compensated Self
Refresh (TCSR)
• Deep Power Down Mode (DPD)
• Double-data rate architecture; two data transfer
per clock cycle
• Bidirectional, data strobe (DQS) is
transmitted/received with data, to be used in
capturing data at the receiver
• DQS edge-aligned with data for READ; center-
aligned with data for WRITE
• Differential clock inputs (CLK and CLK# )
• Commands entered on each positive CLK edge
• Data mask (DM) for write data – one mask per byte
• Bidirectional data strobe per byte of data (DQS)
• Clock Stop capability
• Concurrent Auto Precharge option is supported
• Status Read Register (SRR)
• 64ms refresh
This Data Sheet may be revised by subsequent versions
1
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/11/29