EN25LF05 Datasheet, PDF (10/30 Pages) Eon Silicon Solution Inc. – 512 Kbit Serial Flash Memory with 4Kbytes Uniform Sector

EN25LF05
Figure 7. Read Status Register Instruction Sequence Diagram
Table 6. Status Register Bit Locations
S7
S6
SRP
0
S5
S4
S3
S2
S1
S0
0
BP2
BP1
BP0
WEL
WIP
Status Register Protect
Reserved Bits
Block Protect Bits
Write Enable Latch
Write In Progress
Note : In OTP mode, SRP bit is served as OTP_LOCK bit.
The status and control bits of the Status Register are as follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no
such cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size
of the area to be software protected against Program and Erase instructions. These bits are written
with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1,
BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected against
Page Program (PP) Sector Erase (SE) and , Block Erase (BE), instructions. The Block Protect (BP2,
BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The
Chip Erase (CE) instruction is executed if, and only if, both Block Protect (BP2, BP1, BP0) bits are 0.
This Data Sheet may be revised by subsequent versions ₁₀ ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2008/06/23