EN71SN10F Datasheet, PDF (1/97 Pages) Eon Silicon Solution Inc. – 1.8V NAND Flash + 1.8V Mobile DDR SDRAM Multi-Chip Package

EN71SN10F
EN71SN10F
1.8V NAND Flash + 1.8V Mobile DDR SDRAM Multi-Chip Package
Features
• Multi-Chip Package
- NAND Flash Density: 1-Gbits
- Mobile DDR SDRAM Density: 512-Mbit
• Device Packaging
- 130 balls FBGA
Area: 8x9 mm; Height: 1.0 mm
• Operating Voltage
- NAND : 1.7V to 1.95V
- Mobile DDR SDRAM : 1.7V to 1.95V
• Operating Temperature :-25 °C to +85 °C
NAND FLASH
• Voltage Supply: 1.8V (1.7V ~ 1.95V )
• Organization
- Memory Cell Array :
(64M + 2M) x 16bit for 1Gb
- Multiplexed address/ data
- Data Register : (1K + 32) x 16bit
• Automatic Program and Erase
- Page Program : (1K + 32) words
- Block Erase : (64K + 2K) words
• Page Read Operation
- Page Size : (1K + 32) words
- Random Read : 25µs (Max.)
- Serial Access : 45ns (Min.)
• Memory Cell: 1bit/Memory Cell
• Fast Write Cycle Time
- Page Program Time : 250µs (Typ.)
- Block Erase Time : 2ms (Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power
Transitions
• Reliable CMOS Floating-Gate Technology
• Endurance:
- 100K Program/Erase Cycles (with 1 bit/264
words ECC)
- Data Retention: 10 Years
• Command Register Operation
• Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
• NOP: 4 cycles
• Cache Program/Read Operation
• Copy-Back Operation
• EDO mode
• OTP Operation
Mobile DDR SDRAM
• Density: 512M bits
• Organization: 8M words x16 bits x 4 banks
• Power supply: V_DD/V_DDQ= 1.70~1.95V
• Speed: 400Mbps (max.) for data rate
• 2KB page size
- Row address: A0 to A12
- Column address: A0 to A9
• Four internal banks for concurrent operation
• Interface: LVCMOS
• Burst Length : 2, 4, 8, or 16
• Burst Type : Sequential and Interleave
• CAS# Latency (CL) : 3
• Precharge: auto precharge option for each
burst access
• Drive Strength: normal, 1/2, 1/4, 1/8
• Refresh: auto Refresh and self-refresh
• Refresh cycles: 8192 cycles/64ms
• Optional Partial Array Self Refresh (PASR)
• Auto Temperature Compensated Self Refresh
(ATCSR) by built-in temperature sensor
• Deep Power Down Mode
• Burst termination by burst stop command and
precharge command
• DLL in not implemented
• Double-data-rate architecture, two data access
per clock cycle
• The high-speed data transfer is realized by the
2 bits prefetch pipelined architecture
• Bidirectional data strobe (DQS) is transmitted
/received with data for capturing data at the
receiver
• DQS edge-aligned with data for READs;
center-aligned with data for WRITEs
• Differential clock inputs (CLK and CLK# )
• Commands entered on each positive CLK edge;
data and data mask referenced to both edges
of DQS
• Data mask (DM) for write data
This Data Sheet may be revised by subsequent versions
1
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22