EN71SN10E Datasheet, PDF (1/87 Pages) Eon Silicon Solution Inc. – 1.8V NAND Flash + 1.8V Mobile DDR SDRAM Multi-Chip Package

EN71SN10E
EN71SN10E
1.8V NAND Flash + 1.8V Mobile DDR SDRAM Multi-Chip Package
Features
• Multi-Chip Package
- NAND Flash Density: 1-Gbits
- Mobile DDR SDRAM Density: 256-Mbit
• Device Packaging
- 107 balls FBGA
Area: 10.5x13 mm; Height: 1.2 mm
• Operating Voltage
- NAND : 1.7V to 1.95V
- Mobile DDR SDRAM : 1.7V to 1.95V
• Operating Temperature :-30 °C to +85 °C
NAND FLASH
• Voltage Supply: 1.7V ~ 1.95V
• Organization
- Memory Cell Array :
(128M + 4M) x 8bit for 1Gb
- Multiplexed address/ data
- Data Register : (2K + 64) x 8bit
• Automatic Program and Erase
- Page Program : (2K + 64) bytes
- Block Erase : (128K + 4K) bytes
• Page Read Operation
- Page Size : (2K + 64) bytes
- Random Read : 25µs (Max.)
- Serial Access : 45ns (Min.)
• Memory Cell: 1bit/Memory Cell
• Fast Write Cycle Time
- Page Program Time : 250µs (Typ.)
- Block Erase Time : 2ms (Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power
Transitions
• Reliable CMOS Floating-Gate Technology
• Endurance:
- 100K Program/Erase Cycles (with 1 bit/528
bytes ECC)
- Data Retention: 10 Years
• Command Register Operation
• Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
• NOP: 4 cycles
• Cache Program/Read Operation
• Copy-Back Operation
• EDO mode
• OTP Operation
Mobile DDR SDRAM
• Density: 256M bits
• Organization: 4M words x16 bits x 4 banks
• Power supply: V_DD/V_DDQ= 1.70~1.95V
• Speed: 400Mbps (max.) for data rate
• Internal pipelined double-data-rate architecture,
two data access per clock cycle
• Bi-directional data strobe (DQS)
• No DLL; CLK to DQS is not synchronized.
• Differential clock inputs (CLK and CLK# )
• Four bank operation
• CAS Latency: 3
• Burst Type : Sequential and Interleave
• Burst Length : 2, 4, 8, 16
• Special function support
- PASR (Partial Array Self Refresh)
- Internal TCSR (Temperature Compensated
Self Refresh)
- DS (Drive Strength)
• All inputs except data & DM are sampled at the
rising edge of the system clock(CLK)
• DQS is edge-aligned with data for READ;
center-aligned with data for WRITE
• Data mask (DM) for write masking only
• Auto & Self refresh
• 7.8us refresh interval (64ms refresh period, 8K
cycle)
• LVCMOS-compatible inputs
This Data Sheet may be revised by subsequent versions
1
or modifications due to changes in technical specifications.
©2012 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2012/12/07