EP5388QI Datasheet, PDF (9/14 Pages) Enpirion, Inc. – 800mA Synchronous Buck Regulator With Integrated Inductor 3mm x 3mm x 1.1mm Package

July 2008
Thermal Shutdown
When excessive power is dissipated in the
chip, the junction temperature rises. Once the
junction temperature exceeds the thermal
EP5388QI
shutdown temperature the thermal shutdown
circuit turns off the converter thus allowing the
device to cool. When the junction temperature
decreases by 15°C, the device will go through
the normal startup process.
Application Information
Table 2. VID voltage select settings.
VS2
VS1
VS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Output Voltage Select
V_OUT
3.3V
2.5V
1.8V
1.5V
1.25V
1.2V
0.8V
User
Selectable
To provide the highest degree of flexibility in
choosing output voltage, the EP5388QI uses a
3 pin VID, or Voltage ID, output voltage select
arrangement. This allows the designer to
choose one of seven preset voltages, or to use
an external voltage divider. Internally, the
output of the VID multiplexer sets the value for
the voltage reference DAC, which in turn is
connected to the non-inverting input of the
error amplifier. This allows the use of a single
feedback divider with constant loop gain and
optimum compensation, independent of the
output voltage selected.
External Voltage Divider
As described above, the external voltage
divider option is chosen by connecting the
VS0, VS1, and VS2 pins to V_IN or logic high.
The EP5388QI uses a separate feedback pin,
V_FB, when using the external divider. V_SENSE
must be connected to V_OUT as indicated in
Figure 4.
V_IN
4.7uF
0603
ENABLE
Vin
VSense
Vout
EP5388QI ^Ra
VS0
VFB
VS1
Rb
VS2
GND
V_OUT
47µF
1206
Figure 4. External Divider application circuit.
The output voltage is nominally selected by the
following formula:
( ) V_OUT
= 0.603V 1+
Ra
Rb
Then R_b is given as:
Table 1 shows the various VS2-VS0 pin logic
states and the associated output voltage
levels. A logic “1” indicates a connection to V_IN
or to a “high” logic voltage level. A logic “0”
indicates a connection to ground or to a “low”
logic voltage level. These pins can be either
hardwired to V_IN or GND or alternatively can be
driven by standard logic levels. Logic low is
defined as V_SX ≤ 0.4V. Logic high is defined as
1.4V ≤ V_SX ≤ V_IN. Any level between these two
values is indeterminate. These pins must not
be left floating.
R ^{= 0.603xRa Ω}
b _{VOUT − 0.603}
R_a must be chosen as nominally 200KΩ to
maintain loop gain. V_OUT can be programmed
over the range of 0.603V to V_IN-0.5V.
Dynamically Adjustable Output
The EP5388QI is designed to allow for
dynamic switching between the seven
predefined VID voltage levels. The inter-
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