EP5388QI Datasheet, PDF (10/14 Pages) Enpirion, Inc. – 800mA Synchronous Buck Regulator With Integrated Inductor 3mm x 3mm x 1.1mm Package

July 2008
EP5388QI
voltage slew rate is optimized to prevent
excess undershoot or overshoot as the output
voltage levels transition. The slew rate is
identical to the soft-start slew rate of 1.5V/mS.
Dynamic transitioning between internal VID
settings and the external divider is not allowed.
Input and Output Capacitors
The input capacitance requirement is 4.7uF
0603 MLCC. Enpirion recommends that a low
ESR MLCC capacitor be used.
A variety of output capacitor configurations are
possible depending on footprint and ripple
requirements. For typical applications, it is
recommended to use a single 47uF 1206
MLCC capacitor. Ripple performance can be
improved by using 2 x 22uF 0805 MLCC
capacitors.
A single 10uF 0805 MLCC can be used if V_OUT
programming is accomplished using an
external resistor divider, with the addition of a
10pF phase lead capacitor as shown in Figure
5. Note that in this configuration, V_SENSE
should NOT be connected to V_OUT. R_a and R_b
values are calculated as shown in the external
voltage divider section.
The Input and the output capacitor must use a
X5R or X7R or equivalent dielectric
formulation. Y5V or equivalent dielectric
formulations lose capacitance with frequency,
bias voltage, and temperature and are not
suitable for switch-mode DC-DC converter
output filter applications.
Contact Enpirion Applications for information
on other output capacitor usage.
V_IN
4.7uF
0603
ENABLE
V_in
V_Sense
Vout
EP5388QI ^Ra
VS0
VFB
VS1
Rb
VS2
GND
V_OUT
10µF
0805
10pF
Figure 5. Applications circuit for C_OUT = 1 x 10uF 0805.
Layout Considerations*
*Optimized PCB layout file is downloadable from the Enpirion website to assure first pass design success.
Refer to figure 6 for the following layout recommendations.
Recommendation 1: The input and output filter capacitors should be placed as close to the
EP5388QI as possible to reduce EMI from input and output loop AC currents. This reduces the
physical area of these AC current loops.
Recommendation 2: The system ground plane should be the first layer immediately below the
surface layer (PCB layer 2). If it is not possible to make PCB layer 2 the system ground plane, a local
ground island should be created on PCB layer 2 under the Enpirion device and including the area
under the input and output filter capacitors. This ground plane, or ground island, should be
continuous and uninterrupted underneath the Enpirion device and the input and output filter
capacitors.
Recommendation 3: The surface layer ground pour should include a “slit” as shown in figure 6 to
separate the input and output AC loop currents. This will help reduce noise coupling from the input
current loop to the output current loop.
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