EV1320QI Datasheet, PDF (15/20 Pages) Enpirion, Inc. – The EV1320QI is a DC to DC converter specifically designed for memory termination applications.

EV1320QI
connected between VDDQ pin and the PGND pin.
Do not connect the capacitors to the AGND
terminal. Do not use Y5V or equivalent dielectric
capacitors. These capacitors lose substantial
capacitance with bias, frequency, and temperature
and are thus not appropriate for use in DCDC
converter applications. Refer to the “Layout
Recommendation” section for guidance on
placement and PCB routing.
Table 1. Recommended Capacitor Configurations
Max I_OUT
1A
2A
CIN
10 µF
22 µF
COUT
10 µF
22 µF
CFLY
22µF
22µF + 10µF
Output Capacitors
A 22µF 4V X5R MLCC capacitor is required at the
output for 2A applications. A 10µF may be used for
under 1A applications. The output capacitor must
be placed at the position closest to the VOUT pins
of the EV1320QI. Either 0603 or 0805 case size is
acceptable. The capacitors should be connected
between VOUT pin and the PGND pin. Do not
connect the capacitors to the AGND terminal. Do
not use Y5V or equivalent dielectric capacitors.
These capacitors lose substantial capacitance with
bias, frequency, and temperature and are thus not
appropriate for use in DCDC converter applications.
This capacitor recommendation assumes that there
is additional bulk and decoupling capacitance at
VTT DIMM leads and the VTT islands. Ensure that
there is at least 100µF of bulk capacitance per amp
of VTT current. If there is not sufficient bulk
capacitance, add additional bulk capacitance to the
output of the EV1320QI. Refer to the “Layout
Recommendation” section for guidance on
placement and PCB routing.
C1N and C1P Capacitors (CFLY)
A 22µF 4V X5R MLCC and a 10µF 4V X5R MLCC
capacitors must be connected between the C1N
and C1P pins for 2A applications. A 22µF may be
used for under 1A applications. The CFLY
capacitor must be placed in the position closest to
the C1N and C1P pins. The C1N and C1P pads
should not be connected to any other plane or
trace. Capacitor case size of 0805 or 0603 is
acceptable. Do not use Y5V or equivalent dielectric
capacitors. These capacitors lose substantial
capacitance with bias, frequency, and temperature
and are thus not appropriate for use in DCDC
converter applications. Refer to the “Layout
Recommendation” section for guidance on
placement and PCB routing.
Parallel Operation
The architecture of the EV1320QI lends itself to
seamless parallel operation. Up to 4 devices can be
paralleled to achieve a VTT current of up to 8A.
Figure 7 shows an example circuit diagram for
parallel operation of three EV1320QIs. The
following guidelines must be followed for proper
parallel operation.
1. The VDDQ inputs should be connected to a
common VDDQ bus.
2. The VOUT connections should be
connected to a common VTT bus.
3. Each EV1320QI device must have its own
input and output capacitors connected close
to the device as described in the input and
output capacitor sections. The input and
output capacitors should be connected to
the local PGND pins on the respective
EV1320QI devices.
4. The C1N-C1P capacitors should only be
connected to their respective EV1320QI
devices. They should not be connected to
any common bus, VIN, VOUT, or any other
signal or plane.
5. All AVIN connections should be tied to a
common 3.3V supply rail. Each EV1320QI
should have its own AVIN filter resistor and
capacitor if required.
6. All ENABLE pins should be tied to a
common enable signal.
7. All soft start pins should be tied together
and a single soft start capacitor should be
used. Each device should NOT have its own
soft start capacitor.
8. All Analog ground (AGND) connections
should be tied together. The single soft start
capacitor should be connected to this
common AGND.
9. All Power ground (PGND) connections
should be tied together through a common
PGND plane. However, each input and
output capacitor compliment should be
connected to the local PGND pins on each
individual EV1320QI device.
10. The devices should be placed such that the
impedance in each path to the load is
equivalent to ensure current balance.
©Enpirion 2012 all rights reserved, E&OE
06831
Enpirion Confidential
April 9, 2012
www.enpirion.com, Page 15
Rev: C