EV1320QI Datasheet, PDF (12/20 Pages) Enpirion, Inc. – The EV1320QI is a DC to DC converter specifically designed for memory termination applications.

Functional Description
EV1320QI
VDDQ/VTT Converter
The EV1320QI is designed to replace low efficiency
linear regulators as well as expensive switch-mode
DCDC memory terminations. The patented
EV1320QI architecture provides efficiencies up to
96% with a solution footprint similar to that of a
linear regulator.
VOUT (VTT) tracks ½VDDQ with ±40mV accuracy
and is compliant with DDR2/3/QDR and low power
DDR4 JEDEC memory termination requirements.
The EV1320QI tracks VDDQ directly so there is no
need for a separate reference voltage or resistor
divider network.
If a VREF signal is needed for the VTT termination,
it can be generated by an external VREF divider
circuit from VDDQ, as shown in Figure 5. The R_VREF
resistors divide the VDDQ voltage by 2 and can be
used as the VREF signal. Choose high accuracy
resistors for R_VREF. If more current is needed for
VREF, the divider signal may be buffered by a
voltage follower as shown in Figure 5. Be sure the
R_VREF resistor values are negligible compared to the
input impedance of the voltage follower to ensure
VREF voltage accuracy.
Figure 5. VREF Divider External Circuit
Soft-Start Operation
The EV1320QI has a programmable soft-start. The
EV1320 can operate with AVIN on, ENABLE high,
and VDDQ ramped up and down. If, however,
VDDQ comes up first, and then the device is
enabled, the soft-start capacitor limits the rise of the
output (VTT). The output (VTT) ramp rate is
determined by the value of the soft start (SS)
capacitor, as shown in Table 1. The soft-start time
begins when ENABLE crosses its threshold until
VTT reaches final value.
Table 1. Typical Soft-Start Capacitance Time Table
(No Load)
SS Capacitance (nF) VTT Rise Time (µs)
27
450
15
265
6.8
140
2.7
70
1
40
0.47
30
0.27
25
0.1
20
NOTE: If a fault condition occurs during normal
operation the output is discharged through a 100Ω
resistor for a period of 1.5mS and then a soft start
cycle is initiated.
Enable Operation
The ENABLE pin provides a means to enable or
disable operation of the part. When enable is pulled
high the device will go through a soft start
sequence. When enable is pulled low such as if the
memory device enters S3 (suspend to RAM), the
output will be discharged through a 100Ω resistor.
Please note that if the equivalent load resistance is
lower than 100Ω, the output will discharge faster.
The ENABLE pin should not be left floating.
Power OK (POK)
The EV1320QI provides an open drain output to
indicate if the output voltage stays within nominally
+/- 10% of VDDQ/2. Within this range, the POK
output is allowed to be pulled high. Outside this
range, POK remains low. However, during
transitions such as enable/disable and fault restart
the POK output will not change state until the
transition is complete for enhanced noise immunity.
The POK has 1mA sink capability for events where
it needs to feed a device with standard CMOS
inputs. When POK is pulled high, the pin leakage
current is as low as 25µA maximum over
temperature. This allows a large pull up resistor
such as 100kΩ to be used for minimal current
consumption in shutdown mode.
©Enpirion 2012 all rights reserved, E&OE
06831
Enpirion Confidential
April 9, 2012
www.enpirion.com, Page 12
Rev: C