EN23F0QI Datasheet, PDF (15/26 Pages) Enpirion, Inc. – 15A Voltage Mode Synchronous Buck PWM

supplies: one for PVIN and the other for AVIN.
Single Input Supply Application (PVIN):
Figure 5. Single Supply Applications Circuit
The EN23F0QI has an internal linear regulator that
converts PVIN to 3.3V. The output of the linear
regulator is provided on the AVINO pin once the
device is enabled. AVINO should be connected to
AVIN on the EN23F0QI. In this application, the
following external components are required: Place
a 1µF, X5R/X7R, capacitor between AVINO and
AGND as close as possible to AVINO. Place a
0.1µF, X5R/X7R, capacitor between AVIN and
AGND as close as possible to AVIN. In addition,
place a resistor (R_VB) between VDDB and AVIN, as
shown in Figure 5. Enpirion recommends
R_VB=4.75kΩ. In this application, ENABLE cannot be
asserted before PVIN. If no external enable signal
is used, tying ENABLE to AVIN meets this
requirement.
Dual Input Supply Application (PVIN and AVIN):
Figure 6: Dual Input Supply Application Circuit
In this application, place a 0.1µF, X7R, capacitor
between AVIN and AGND as close as possible to
AVIN. Refer to Figure 6 for a recommended
EN23F0QI
schematic for a dual input supply application.
For dual input supply applications, the sequencing
of the two input supplies, PVIN and AVIN, is very
important. During power up, neither ENABLE nor
PVIN should be asserted before AVIN. There are
two common acceptable turn-on/off sequences for
the device. ENABLE can be tied to AVIN and come
up with it, and PVIN can be ramped up and down
as needed. Alternatively, PVIN can be brought high
after AVIN is asserted, and the device can be
turned on and off by toggling the ENABLE pin.
PVIN may be applied before AVIN if ENABLE is
toggled after both PVIN and AVIN is applied.
Enable Operation
The ENABLE pin provides a means to enable
normal operation or to shut down the device. A
logic high will enable the converter into normal
operation. When the ENABLE pin is asserted (high)
the device will undergo a normal soft-start, allowing
the output voltage to rise monotonically into
regulation. A logic low will disable the converter and
the device will power down in a controlled manner.
The ENABLE signal has to be low for at least the
ENABLE Lockout Time (8ms) in order for the
device to be re-enabled.
Pre-Bias Precaution
The EN23F0QI is not designed to be turned on into
a pre-biased output voltage. Be sure the output
capacitors are not charged or the output of the
EN23F0QI is not pre-biased when the EN23F0QI
is first enabled.
Frequency Synchronization
The switching frequency of the EN23F0QI can be
phase-locked to an external clock source to move
unwanted beat frequencies out of band. The
internal switching clock of the EN23F0QI can be
phase locked to a clock signal applied to the S_IN
pin. An activity detector recognizes the presence of
an external clock signal and automatically phase-
locks the internal oscillator to this external clock.
Phase-lock will occur as long as the input clock
frequency is in the range of 0.8MHz to 1.6MHz.
When no clock is present, the device reverts to the
free running frequency of the internal oscillator.
Adding a resistor (R_FS) to the FADJ pin will adjust
the switching frequency. If a 3KΩ resistor is placed
on FADJ the nominal switching frequency of the
EN23F0QI is 1MHz. Figure 7 shows the typical R_FS
resistor value versus switching frequency.
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Enpirion Confidential
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