H4006 Datasheet, PDF (7/10 Pages) EM Microelectronic - MARIN SA – 13.56MHz 64 Data bit Read Only Contactless Identification Device

EM MICROELECTRONIC-MARIN SA H4006
RF Interface
Resonant capacitor, Rectifier, Limiter and
Modulator Switch form the unit which is
interfacing to the incoming RF signal. These
blocks are interdependent so they are developed
as unit. They interface to the antenna which
typical characteristics are:
Ls ≈ 1400 nH
Rs ≈ 3 Ohms
30 < Q < 40 at 13.56 MHz.
Resonant Capacitor
The capacitor value is adjusted by laser fusing. It
can be trimmed in factory by 1pF steps to
achieve the absolute value of 94.5pF typically.
This option, which is available on request, allows
a smaller capacitor tolerance over the whole
production.
Rectifier and Limiter
A full wave rectifier (Graetz Bridge) is used to
provide supply voltage to the IC. The reverse
breakdown of the diodes is also used to protect
the IC from overvoltages.
Modulator Switch
Due to the low impedance of the antenna and
resonant capacitor the Modulator Switch has to
present low RF impedance when switched ON
(about 100 ohms).
The minimum time period with the Modulator
Switch ON is 38 µs. At lower data rates this time
is even much longer. The current consumption of
divider chain running at 13 MHz is near 60 µA.
Putting together this two figures it is clear that it is
not possible to supply the IC during the time the
Modulator Switch is ON from the integrated
Supply Buffer Capacitor which value is
approximately 140 pF. The IC has to get power
from the RF field also during the time the
Modulator Switch is ON.
This problem is solved by putting the Modulator
Switch on the output of the Rectifier (between
VDD and VSS) and regulating its ON resistance in
function of supply voltage. When the supply
voltage is high the ON impedance is low. When
the supply voltage drops near the region where
the operation of the IC at 13.56 MHz is not
guaranteed the ON impedance is increased in
order to prevent further drop.
NRZ-L
STREAM
10 11 000 11 01
DM-M
CODED
Bit i-1 Bit i
x
1
0
0
1
0
no transition at the beginning of Bit i,
transition at the beginning of Bit i,
no transition at the beginning of Bit i,
transition in the middle of Bit i
no transition in the middle of Bit i
no transition in the middle of Bit i
Figure 6
7