EM47FM3288SBB Datasheet, PDF (39/41 Pages) Eorex Corporation – 16Gb (64M×8Bank×32) Double DATA RATE 3 Stack SDRAM

EM47FM3288SBB
Mode Register MR3
The Mode Register MR3 controls Multi Purpose Registers (MPR). The Mode Register 3 is written by asserting
low on CS, RAS, CAS, WE, high on BA1 and BA0, and low on BA2 while controlling the states of address pins
according to the table below.
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
MPR MPR Location
MPR Operation A2
Normal operation 0
Dataflow from MPR 1
MRS Mode
MR0
MR1
MR2
MR3
BA1 BA0
0
0
0
1
1
0
1
1
MPR Location
Predefined pattern
Reserved
Reserved
Reserved
A1 A0
0
0
0
1
1
0
1
1
Note1. BA2, A3 - A13 are reserved for future use (RFU) and must be programmed to 0 during MRS.
Note2. The predefined pattern will be used for read synchronization.
Note3. When MPR control is set for normal operation, MR3 A[2] = 0, MR3 A[1:0] will be ignored
Multi Purpose Register (MPR)
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit
sequence. To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with
bit A2 = 1. Prior to issuing the MRS command, all banks must be in the idle state (all banks precharged and
tRP met). Once the MPR is enabled, any subsequent RD or RDA commands will be redirected to the Multi
Purpose Register. When the MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS
command is issued with the MPR disabled (MR3 bit A2 = 0). Power-down mode, self-refresh and any other
non-RD/RDA command is not allowed during MPR enable mode. The RESET function is supported during
MPR enable mode.
Jul. 2012
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