EM47FM3288SBB Datasheet, PDF (18/41 Pages) Eorex Corporation – 16Gb (64M×8Bank×32) Double DATA RATE 3 Stack SDRAM

EM47FM3288SBB
AC Operating Test Characteristics
DDR3-1333 & DDR3-1600 Speed Bins
(VDD, VDDQ=1.5V±0.075V)
Symbol
Speed Bin
CL-nRCD-nRP
-125
(DDR3-1600)
11-11-11
-150
(DDR3-1333)
9-9-9
Units Notes
Parameter
Min. Max. Min. Max.
t_AA
t_RCD
t_RP
t_RC
t_RAS
t_{CK (AVG)}
Internal read command to first data
Active to read or write delay
Precharge command period
Active to active/auto refresh command
Active to precharge command period
Average Clock Cycle, CL=6, CWL=5
13.125 20
13.5
20
ns
8
13.125
-
13.5
-
ns
8
13.125
-
13.5
-
ns
8
48.75
-
49.5
-
ns
8
35
9*t_REFI
36
9*t_REFI ns
7
2.5
3.3
2.5
3.3
ns
1,2,3,5
.6
t_{CK (AVG)} Average Clock Cycle, CL=7, CWL=6
1.875 2.5 1.875 2.5
ns
1,2,3,4
,5,6
t_{CK (AVG)} Average Clock Cycle, CL=8, CWL=6
1.875 2.5 1.875 2.5
ns
1,2,3,5
,6
t_{CK (AVG)} Average Clock Cycle, CL=9, CWL=7
1.5
1.875
1.5
1.875
ns
1,2,3,4
,6
t_{CK (AVG)}
t_{CK (AVG)}
-
Average Clock Cycle, CL=10, CWL=7
Average Clock Cycle, CL=11, CWL=8
Support CL Settings
1.5 1.875
1.25
1.5
6,7,8,9,10,11
1.5 1.875
-
-
6,7,8,9,10
ns 1,2,3,6
ns 1,2,3
nCK
-
Support CWL Settings
5,6,7,8
5,6,7
nCK
Notes1. The CL setting and CWL setting result in tCK (avg) (min.) and tCK (avg) (max.) requirements. When
making a selection of tCK (avg), both need to be fulfilled: Requirements from CL setting as well as
requirements from CWL setting.
Notes2. tCK (avg) (min.) limits: Since /CAS latency is not purely analog - data and strobe output are
synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application
should use the next smaller JEDEC standard tCK (avg) value (2.5, 1.875, 1.5, or 1.25ns) when
calculating CL (nCK) = tAA (ns) / tCK (avg)(ns), rounding up to the next ‘Supported CL’.
Notes3. tCK (avg) (max.) limits: Calculate tCK (avg) + tAA (max.)/CL selected and round the resulting tCK (avg)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875ns or 1.25ns). This result is tCK (avg)
(max.) corresponding to CL selected.
Notes4. ‘Reserved’ settings are not allowed. User must program a different value.
Notes5. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the
table DDR3-1333 Speed Bins which is not subject to production tests but verified by
design/characterization.
Notes6. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the
table DDR3-1600 Speed Bins which is not subject to production tests but verified by
design/characterization.
Notes7. tREFI depends on operating case temperature (TC).
Notes8. For devices supporting optional down binning to CL = 7 and CL = 9, tAA/tRCD/tRP(min.) must be
13.125 ns or lower. SPD settings must be programmed to match.
Jul. 2012
18/41
www.eorex.com