V6116 Datasheet, PDF (11/15 Pages) EM Microelectronic - MARIN SA – Digitally Programmable 2, 4 and 8 Mux LCD Driver

R
the V6116 8. A selected row (on) is in phase with the FR
signal (see Fig. 7, 8 and 9).
It is recommended that data transfer to the V6116 should
be synchronized to the FR signal to avoid a falling or
rising edge on the FR signal while writing data to the
V6116. The LCD pixels change polarity with the FR
signal. On the edges of the FR signal current spikes will
appear on the V_SS and V_LCD supply lines. If the supply
lines have high impedance then voltage spikes will
appear. These voltage spikes could interfere with data
loading on the DI and CLK pins. The V6116 has filters in
order to reduce perturbation on the input signals.
It is also recommended that data transfer to the V6116
should be synchronized to the FR signal to avoid DC
component which may especially appear during Blink
function.
Driver Outputs S1 to S40
There are 40 LCD driver outputs on the V6116. When
COL is inactive, the outputs S1 to Sn function as row
drivers and the outputs S(n+1) to S40 function as column
drivers, where n is the V6116 mux mode no. (2, 4 or 8).
When COL is active, all 40 outputs function as column
drivers (see Table 6). There is a one to one relationship
between the display selected RAM and the LCD driver
outputs. Each pixel (segment) driven by the V6116 on the
LCD has a display RAM bit which corresponds to it.
Setting the bit turns the segment "on" and clearing it turns
it "off".
V6116
COL Input
The V6116 functions as a row and column driver while the
COL input is inactive. When active, the COL input
configures the V6116 to function as a column driver only.
The former row outputs function as column outputs. In
cascaded applications, one V6116 should be used in the
row and column configuration ( COL inactive) and the rest
as pure column drivers ( COL active) (see Fig. 10).
Note: when cascading V6116s never cascade one mux
mode no. with another. If a V6116 mux mode 8 is used to
drive the rows, then only V6116s mux mode 8 can be
cascaded with it (see Fig. 10).
Power Up
On power up the data in the shift registers, the two display
RAMs and the 40 bit display latches are undefined. The
STR input and the command bit 7 should be taken high on
power up to blank the display, then the display data
written to the display selected RAM (see Fig. 11). When
finished the initial write to the display selected RAM, take
the STR input low to display the display selected RAM
contents (see also section "STR Input").
Applications
Two V6116 Mux Mode 8 Cascaded
By connecting the V1, V2 and V3 bias outputs as shown, the pixel load is averaged across all the drivers. The
effective bias level source impedance is the parallel combination of the total number of drivers. For example, if
two V6116 are cascaded as above, then the maximum bias level impedance becomes 12.5 kΩ.
Fig. 10
Copyright © 2005, EM Microelectronic-Marin SA
11
www.emmicroelectronic.com