EMD12324P Datasheet, PDF (9/44 Pages) Emerging Memory & Logic Solutions Inc – 512M: 16M x 32 Mobile DDR SDRAM

Preliminary
EMD12324P
512M: 16M x 32 Mobile DDR SDRAM
Table 8: OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Sym-
bol
-60
Min
Max
DQ output access time from CK/CKB
t_AC
2
5
DQS output access time from CK/CKB
t_DQSCK
2
5
Clock high-level width
t_CH
0.45
0.55
Clock low-level width
t_CL
0.45
0.55
Clock half period
t_HP
min
(t_CL,t_CH)
Clock cycle time
CL = 3
6
100
t_CK
CL = 2
9
100
DQ and DM input setup time
t_DS
1.0
DQ and DM input hold time
t_DH
1.0
DQ and DM input pulse width
t_DIPW
1.8
Address and control input setup time
t_IS
1.1
Address and control input hold time
t_IH
1.1
Address and control input pulse width
t_IPW
2.6
DQ & DQS low-impedance time from CK/CKB
t_LZ
1.0
DQ & DQS high-impedance time from CK/CKB
t_HZ
5
DQS - DQ skew
t_DQSQ
0.6
DQ / DQS output hold time from DQS
t_QH t_HP-t_QHS
Data hold skew factor
t_QHS
0.65
Write command to 1st DQS latching transition
t_DQSS 0.75
1.25
DQS input high-level width
t_DQSH
0.4
0.6
DQS input low-level width
t_DQSL
0.4
0.6
DQS falling edge to CK rising - setup time
t_DSS
0.2
DQS falling edge from CK rising - hold time
t_DSH
0.2
MODE REGISTER SET command period
t_MRD
2
Write preamble setup time
t_WPRES
0
Write postamble
t_WPST
0.4
0.6
Write preamble
t_WPRE 0.25
-75
Min
Max
2.5
6.0
2.5
6.0
0.45
0.55
0.45
0.55
min
(t_CL,t_CH)
7.5
100
12
100
1.0
1.0
2.0
1.3
1.3
2.6
1.0
6.0
0.6
t_HP-t_QHS
0.75
0.75
1.25
0.4
0.6
0.4
0.6
0.2
0.2
2
0
0.4
0.6
0.25
Unit Note
ns 3
ns
t_CK
t_CK
ns
ns
ns
ns 4,5
ns 4,5
ns
ns 1
ns 1
ns
ns
ns
ns
ns
ns
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
ns
t_CK
t_CK
9
Rev 0.0