EMC326SP16AJ Datasheet, PDF (53/64 Pages) Emerging Memory & Logic Solutions Inc – 2Mx16 bit CellularRAM

Preliminary
EMC326SP16AJ
2Mx16 CellularRAM
Figure 42. Burst WRITE Row boundary crossing
V_IH
CLK
V_IL
V_IH
A[20:0]
V_IL
V_IH
ADV#
V_IL
V_IH
UB#/LB#
V_IL
V_IH
CE#
V_IL
OE# ^VIH
V_IL
V_IH
WE#
V_IL
V_IH
DQ[15:0]
V_IL
V_OH
WAIT
V_OL
t_CLK
t_SP
t_HD
Valid input
End of row
Valid input Valid input
t_KTHL
t_KOH
Note 2
t_KTHL
t_KOH
Valid output Valid output
Don’t Care
Note:
1. Non-default BCR settings for burst WRITE at end of row : Fixed or variable latency, WAIT active LOW, WAIT asserted during delay. (shown as
solid line)
2. WAIT will be assert for LC or LC + 1 cycles for variables latency, or LC cycles for fixed latency.
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