EMC646SP16K Datasheet, PDF (4/52 Pages) Emerging Memory & Logic Solutions Inc – 4Mx16 bit CellularRAM AD-MUX

Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
List of Figures
Figure 1: Functional Block Diagram - 4 Meg x 16 ............................................................................................................................. 6
Figure 2: Power-Up Initialization Timing ........................................................................................................................................... 9
Figure 3: READ Operation ................................................................................................................................................................ 11
Figure 4: WRITE Operation .............................................................................................................................................................. 11
Figure 5: Burst Mode READ(4-word burst)........................................................................................................................................ 12
Figure 6: Burst Mode WRITE (4-word burst)...................................................................................................................................... 13
Figure 7: Refresh Collision During Variable-Latency READ Operation ............................................................................................. 14
Figure 8: Wired-OR WAIT Configuration ........................................................................................................................................... 15
Figure 9: Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation .......................................... 17
Figure 10: Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation ............................................ 18
Figure 11: Register READ, Asynchronous Mode, Followed by READ ARRAY Operation .................................................................. 19
Figure 12: Register READ, Synchronous Mode, Followed by READ ARRAY Operation .................................................................... 20
Figure 13: Load Configuration Register .............................................................................................................................................. 22
Figure 14: Read Configuration Register ............................................................................................................................................. 22
Figure 15: Bus Configuration Register Definition ................................................................................................................................ 23
Figure 16: WAIT Configuration During Burst Operation ...................................................................................................................... 26
Figure 17: Latency Counter (Variable Initial Latency, No Refresh Collision) ....................................................................................... 27
Figure 18: Latency Counter (Fixed Latency) ....................................................................................................................................... 27
Figure 19: Refresh Configuration Register Mapping ........................................................................................................................... 28
Figure 20: AC Input / Output Reference Waveform ............................................................................................................................ 31
Figure 21: AC Output Load Circuit ...................................................................................................................................................... 31
Figure 22: Initialization Period ............................................................................................................................................................ 36
Figure 23: Asynchronous READ ......................................................................................................................................................... 36
Figure 24: Single-Access Burst READ Operation - Variable Latency ................................................................................................. 37
Figure 25: 4-Word Burst READ Operation - Variable Latency ............................................................................................................. 38
Figure 26: Single-Access Burst READ Operation - Fixed Latency ...................................................................................................... 39
Figure 27: 4-Word Burst READ Operation - Fixed Latency ................................................................................................................. 40
Figure 28: Burst READ Terminate at End-of-Row (Wrap off) .............................................................................................................. 41
Figure 29: Burst READ Row Boundary Crossing ................................................................................................................................ 42
Figure 30: Asynchronous WRITE ....................................................................................................................................................... 43
Figure 31: Burst WRITE Operation - Variable Latency Mode ............................................................................................................. 44
Figure 32: Burst WRITE Operation - Fixed Latency Mode .................................................................................................................. 45
Figure 33: Burst WRITE Terminate at End-of-Row (Wrap off) ............................................................................................................ 46
Figure 34: Burst WRITE Row Boundary Crossing .............................................................................................................................. 47
Figure 35: Burst WRITE Followed by Burst READ .............................................................................................................................. 48
Figure 36: Asynchronous WRITE Followed by Burst READ ............................................................................................................... 49
Figure 37: Burst READ Followed by Asynchronous WRITE ............................................................................................................... 50
Figure 38: Asynchronous WRITE Followed by Asynchronous READ ................................................................................................. 51
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