EMC646SP16K Datasheet, PDF (28/52 Pages) Emerging Memory & Logic Solutions Inc – 4Mx16 bit CellularRAM AD-MUX

Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Operating Mode (BCR[15]) Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation.
REFRESH CONFIGURATION REGISTER
The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh
parameters can dramatically reduce current consumption during standby mode. Figure 19 describes the control bits used in the RCR. At
power-up, the RCR is set to 0010h. The RCR is accessed with CRE HIGH and A[19:18] = 00b; or through the register access software
sequence with A/DQ = 0000h on the third cycle.
Figure 19: Refresh Configuration Register Mapping
A[21:20]
A[19:18]
A[17:16]
A/DQ
[15:7]
A/DQ
6
A/DQ
5
A/DQ
4
A/DQ
3
A/DQ
2
A/DQ
1
A/DQ
0
21~20
Reserved
19-18
Register Select
17-16
Reserved
15~7
Reserved
All must be set to “0”
All must be set to “0”
RCR[19]
0
1
0
RCR[18]
0
0
1
Register Select
Select RCR
Select BCR
Select DIDR
6
5
4
3
2
1
0
Ignored
Reserved
PAR
Setting is ignored
(Default 001b)
Must be set to “0”
RCR[2]
0
0
0
0
1
1
1
1
RCR[1]
0
0
1
1
0
0
1
1
RCR[0]
0
1
0
1
0
1
0
1
Refresh Coverage
Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
Top 1/2 array
Top 1/4 array
Top 1/8 array
Note: 1. Reserved bits must be set to zero. Reserved bits not set to zero will affect device functionality. RCR[15:0] will be read back as written.
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