EM77930 Datasheet, PDF (90/114 Pages) ELAN Microelectronics Corp – USB + BB Controller

EM77930
USB+BB Controller
9.5.16 Endpoint n Count Register (EPnCTR)
Endpoint 1 count Register (EP1CTR)
Endpoint 2 count Register (EP2CTR)
Endpoint 3 count Register (EP3CTR)
Bit
Field HW SW DF
Description
RX Byte Count (Bulk Out / Isochronous Out)
When receive enable is set to 1, this field specifies
the receive byte counts in the receive FIFO.
0-7 EPnCT R/W R/W 0 ^{TX Byte Count (Interrupt In / Bulk In / Isochronous In)}
When transmit enable is set to 1, this field specifies
the transmit byte counts in the transmit FIFO. HW
always accesses the FIFO from Address 0.
This register will be reset by USB reset or SW reset.
7 Reserved
9.5.17 Endpoint n Data Register (EPnDAR)
Endpoint 1 Data Register (EP1DAR)
Endpoint 2 Data Register (EP2DAR)
Endpoint 3 Data Register (EP3DAR)
Bit Field HW SW DF
Description
RX Data (Bulk Out / Isochronous Out)
Receive FIFO data will be read by SW through
0-7
DATA
R/W
R or
W
0
reading this register.
TX Data (Interrupt In / Bulk In / Isochronous In)
SW writes data to this register will be written to
transmit FIFO.
9.5.18 USB Device SOF Event Register (HINTR)
Bit
Field
HW SW DF
Description
0-5 Reserved
6
SOFINT
R/W R/W0C 0
Start of frame interrupt. Asserted after the receipt
of a valid SOF.
7 Reserved
9.5.19 USB Device SOF Event Enable Register (HINTE)
Bit
Field
HW SW DF
Description
0-5 Reserved
6 SOFINTE R R/W 0 SOF Interrupt Event Enable.
7 Reserved
9.5.20 Frame Number Low-Byte Register (FNLR)
Bit
Field
HW SW DF
Description
0-7
FNLR R/W R 0 Bits 0~7 of Frame Number (11 bits)
9.5.21 Frame Number High-Byte Register (FNHR)
Bit
Field
HW SW DF
Description
0-2
FNHR R/W R 0 Bits 8~10 of Frame Number (11 bits)
3-7 Reserved
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Product Specification (V1.0) 08.20.2007
(This specification is subject to change without further notice)