EM77930 Datasheet, PDF (89/114 Pages) ELAN Microelectronics Corp – USB + BB Controller

EM77930
USB+BB Controller
Bit Field
HW SW DF
Description
3 DTOGERR R/W R
Data Toggle Error (Interrupt OUT / Bulk OUT)
Reserved (Interrupt In / Bulk In / Isochronous IN /
Isochronous OUT)
0
Set by HW to indicate toggle error occurs.
Cleared when SW writes a 0 to clear the EPn OUT
event interrupt status.
4 ACKSTS R/W R
ACK Status
Set by HW when a transaction is completed with
0 _{ACK handshake. This bit will be updated}
automatically at the next valid transaction (ends
with ACK or STALL).
5 STALLSTS R/W R
STALL Status
Set by HW when a transaction is completed with
0 _{STALL handshake. This bit will be updated}
automatically at the next valid transaction (ends
with ACK or STALL).
6 ERRSTS R/W R
Error Status
Set by HW to indicate either USB PID error, CRC
error, bit stuffing error, time out without handshake
0 response from USB host (for IN transaction) or no
data phase from USB host occur (OUT transaction).
This bit will be updated automatically at the next
valid transaction (ends with ACK or STALL).
7 CDTOG R/W0C W
Clear endpoint Toggle.
0
When SW writes 1 to this bit, it will clear the DTOG
bit which is in the same register.
Reserved (Isochronous IN or Isochronous OUT)
The following table lists the meaning of the Endpoint n command/status Register
(EPnCSR) for different Endpoint-Type.
Bit Interrupt IN Interrupt OUT Bulk IN
RXTXEN RXTXEN
RXTXEN
0
(TX Enable) (RX Enable) (TX Enable)
1 SESTALL SESTALL SESTALL
2 DTOG
DTOG
DTOG
3 Reserved DTOGERR Reserved
4 ACKSTS ACKSTS
ACKSTS
5 STALLSTS STALLSTS STALLSTS
6 ERRSTS ERRSTS
ERRSTS
7 CDTOG
CDTOG
CDTOG
Bulk OUT
RXTXEN
(RX Enable)
SESTALL
DTOG
DTOGERR
ACKSTS
STALLSTS
ERRSTS
CDTOG
Isochronous Isochronous
IN
OUT
RXTXEN RXTXEN
(TX Enable) (RX Enable)
Reserved Reserved
Reserved Reserved
Reserved Reserved
ACKSTS ACKSTS
STALLSTS STALLSTS
ERRSTS ERRSTS
Reserved Reserved
Product Specification (V1.0) 08.20.2007
• 81
(This specification is subject to change without further notice)