EDJ1104BDSE Datasheet, PDF (94/147 Pages) Elpida Memory – 1G bits DDR3 SDRAM

EDJ1104BDSE, EDJ1108BDSE
Register Address Table
The table below provides an overview of the available data locations, how they are addressed by MR3 A [1:0] during
a MR0 to MR3, and how their individual bits are mapped into the burst order bits during a multi purpose register
read.
[Available Data Locations and Burst Order Bit Mapping for Multi Purpose Register]
MR3
A [2]
MR3
A [1:0]
Function
Burst
Length
Read
Address Burst Order and Data Pattern
A [2:0]
Read
BL8
000
Burst order 0,1,2,3,4,5,6,7
Pre-defined pattern [0,1,0,1,0,1,0,1]
predefined
1
00
pattern for
BC4
system
000
Burst order 0,1,2,3,
Pre-defined pattern [0,1,0,1]
calibration
BC4
100
Burst order 4,5,6,7
Pre-defined pattern [0,1,0,1]
BL8
000
Burst order 0,1,2,3,4,5,6,7
Notes
1
1
1
1
1
01
RFU
BC4
000
Burst order 0,1,2,3
1
BC4
100
Burst order 4,5,6,7
1
BL8
000
Burst order 0,1,2,3,4,5,6,7
1
1
10
RFU
BC4
000
Burst order 0,1,2,3
1
BC4
100
Burst order 4,5,6,7
1
BL8
000
Burst order 0,1,2,3,4,5,6,7
1
1
11
RFU
BC4
000
Burst order 0,1,2,3,
1
BC4
100
Burst order 4,5,6,7
1
Note: 1. Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
Relevant Timing Parameters
The following AC timing parameters are important for operating the Multi Purpose Register: tRP, tMRD, tMOD and
tMPRR.
Besides these timings, all other timing parameters needed for proper operation of the DDR3 SDRAM need to be
observed.
[MPR Recovery Time tMPRR]
Symbol
Description
tMPRR
Multi Purpose Register Recovery Time, defined between end of MPR read burst and MRS which
reloads MPR or disables MPR function
Preliminary Data Sheet E1494E50 (Ver. 5.0)
94