EDJ1104BDSE Datasheet, PDF (89/147 Pages) Elpida Memory – 1G bits DDR3 SDRAM

EDJ1104BDSE, EDJ1108BDSE
Extended Temperature Usage (MR2)
[Mode Register Description]
Field Bits Description
0
ASR A6 ₁
Manual SR Reference (SRT)
ASR enable (optional)
0
SRT A7
1
Normal operating temperature range
Extended operating temperature range
Description
Auto self-refresh (ASR) (Optional)
when enabled, DDR3 SDRAM automatically
provides self-refresh power management
functions for all supported operating
temperature values. If not enabled, the SRT
bit must be programmed to indicate TC during
subsequent self-refresh operation
Self-Refresh Temperature (SRT) Range
If ASR = 0, the SRT bit must be programmed
to indicate TC during subsequent self-refresh
operation
If ASR = 1, SRT bit must be set to 0
Partial Array Self-Refresh (PASR)
Optional in DDR3 SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine
if DDR3 SDRAM devices support the following options or requirements referred to in this material. If PASR (Partial
Array Self-Refresh) is enabled, data located in areas of the array beyond the specified address range shown in
figure of MR2 programming will be lost if Self-Refresh is entered. Data integrity will be maintained if tREFI
conditions are met and no Self-Refresh command is issued.
/CAS Write Latency (CWL)
The /CAS Write Latency is defined by MR2 bits [A3, A5], as shown in figure of MR2 programming. /CAS Write
Latency is the delay, in clock cycles, between the internal Write command and the availability of the first bit of input
data. DDR3 SDRAM does not support any half-clock latencies. The overall Write Latency (WL) is defined as
Additive Latency (AL) + /CAS Write Latency (CWL); WL = AL + CWL. For more information on the sup-ported CWL
and AL settings based on the operating clock frequency, refer to “Standard Speed Bins”. For detailed Write operation
refer to “WRITE Operation”.
Auto Self-Refresh Mode - ASR Mode (optional)
DDR3 SDRAM provides an Auto Self-Refresh mode (ASR) for application ease. ASR mode is enabled by setting
MR2 bit A6 = 1 and MR2 bit A7 = 0. The DRAM will manage self-refresh entry in either the Normal or Extended
(optional) Temperature Ranges. In this mode, the DRAM will also manage self-refresh power consumption when the
DRAM operating temperature changes, lower at low temperatures and higher at high temperatures.
If the ASR option is not supported by the DRAM, MR2 bit A6 must be set to 0.
If the ASR mode is not enabled (MR2 bit A6 = 0), the SRT bit (MR2 A7) must be manually programmed with the
operating temperature range required during self-refresh operation.
Support of the ASR option does not automatically imply support of the Extended Temperature Range.
Self- Refresh Temperature Range - SRT
If ASR = 0, the Self-Refresh Temperature (SRT) Range bit must be programmed to guarantee proper self-refresh
operation. If SRT = 0, then the DRAM will set an appropriate refresh rate for self-refresh operation in the Normal
Temperature Range. If SRT = 1 then the DRAM will set an appropriate, potentially different, refresh rate to allow
self-refresh operation in either the Normal or Extended Temperature Ranges. The value of the SRT bit can effect
self-refresh power consumption, please refer to the IDD table for details.
For parts that do not support the Extended Temperature Range, MR2 bit A7 must be set to 0 and the DRAM should
not be operated outside the Normal Temperature Range.
Preliminary Data Sheet E1494E50 (Ver. 5.0)
89