EDW1032BBBG Datasheet, PDF (8/16 Pages) Elpida Memory – 1G bits GDDR5 SGRAM

EDW1032BBBG
1.4 Clocking
The GDDR5 SGRAM operates from a differential clock CK and /CK. Commands are registered at every rising edge
of CK. Addresses are registered at every rising edge of CK and every rising edge of /CK.
GDDR5 uses a double data rate data interface and an 8n-prefetch architecture. The data interface uses two
differential forwarded clocks (WCK, /WCK). DDR means that the data is registered at every rising edge of WCK and
rising edge of /WCK. WCK and /WCK are continuously running and operate at twice the frequency of the
command/address clock (CK, /CK).
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Figure 1: GDDR5 Clocking and Interface Relationship
1.5 Addressing
The GDDR5 SGRAM uses a double data rate address scheme to reduce pins required on the GDDR5 SGRAM as
shown in Table 4. The addresses should be provided to the GDDR5 SGRAM in two parts; the first half is latched on
the rising edge of CK along with the command pins such as /RAS, /CAS and /WE; the second half is latched on the
rising edge of /CK.
The use of DDR addressing allows all address values to be latched in at the same rate as the SDR commands. All
addresses related to command access have been positioned for latching on the initial rising edge for faster
decoding.
Table 4: Address Pairs
Clock Edge
Rising CK
Rising /CK
Address Inputs
BA3
BA2
BA1
BA0
A11
A10
A9
A8
A3
A4
A5
A2
A6
A0
A1
A7
Addressing schemes for x32 mode and x16 mode differ only in the number of valid column addresses, as shown in
Table 5.
Table 5: Addressing Scheme
Row Address
Column address
Bank address
Autoprecharge
Page size
Refresh
Refresh period
32M x 32
A0-A11
A0-A5
BA0-BA3
A8
2 KB
8k/32ms
3.9 µs
64M x 16
A0-A11
A0-A6
BA0-BA3
A8
2 KB
8k/32ms
3.9 µs
Data Sheet E1771E11 (Ver. 1.1)
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