EDW1032BBBG Datasheet, PDF (1/16 Pages) Elpida Memory – 1G bits GDDR5 SGRAM

DATA SHEET
1G bits GDDR5 SGRAM
EDW1032BBBG (32M words x 32 bits)
Specifications
Features
• Density: 1G bits
• Organization
— 2Mbit x 32 I/O x 16 banks
— 4Mbit x 16 I/O x 16 banks
• Package
— 170-ball FBGA
— Lead-free (RoHS compliant) and Halogen-free
• Power supply:
— VDD: 1.5V ±3% and 1.35V ± 3%
— VDDQ: 1.5V ±3% and 1.35V ±3%
• Data rate: 7.0Gbps/6.0Gbps/5.0Gbps/4.0Gbps (max.)
• 16 internal banks
• Four bank groups for tCCDL = 3tCK
• 8n prefetch architecture: 256 bit per array Read or
Write access; 128 bit for x16
• Burst length (BL): 8 only
• Programmable CAS latency: 6 to 20
• Programmable Write latency: 3 to 7
• Programmable CRC READ latency: 0 to 3
• Programmable CRC WRITE latency: 8 to 14
• Programmable EDC hold pattern for CDR
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/32ms
• Interface: Pseudo open drain (POD-15)
• On-die termination (ODT): nom. values of 60Ω or 120Ω
• Pseudo open drain (POD-15) compatible outputs
— 40Ω pulldown
— 60Ω pullup
• ODT and output driver strength auto-calibration with
external resistor ZQ pin (120Ω)
• Programmable termination and driver strength offsets
• Selectable external or internal VREF for data inputs;
programmable offsets for internal VREF
• Separate external VREF for address / command inputs
• Operating case temperature range
— TC = 0°C to +95°C
• x32/x16 mode configuration set at power-up with
EDC pin
• Single ended interface for data, address and command
• Quarter data-rate differential clock inputs CK, /CK for
address and commands
• Two half data-rate differential clock inputs WCK, /WCK,
each associated with two data bytes (DQ, /DBI, EDC)
• Double Data Rate (DDR) data (WCK)
• Single Data Rate (SDR) command (CK)
• Double Data Rate (DDR) addressing (CK)
• Write data mask function via address bus
(single/double byte mask)
• Data Bus Inversion (DBI) and Address Bus Inversion
(ABI)
• Input/output PLL on/off mode
• Address training: address input monitoring via DQ pins
• WCK2CK clock training: phase information via EDC
pins
• Data read and write training via Read FIFO (FIFO
depth = 6)
• Read FIFO pattern preload by LDFF command
• Direct write data load to Read FIFO by WRTR
command
• Consecutive read of Read FIFO by RDTR command
• Read/Write data transmission integrity secured by
cyclic redundancy check (CRC–8)
• Read/Write EDC on/off mode
• DQ Preamble for Read on/off mode
• Low Power modes
• RDQS mode on EDC pin
• On-chip temperature sensor with read-out
• Automatic temperature sensor controlled self-refresh
rate
• Digital tRAS lockout
• Vendor ID, FIFO depth and Density info fields for
identification
• Mirror function with MF pin
• Boundary Scan function with SEN pin
Document No. E1771E11 (Ver. 1.1)
Date Published September 2011 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2011